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A32: Implement ASIMD VMUL (scalar)

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This commit is contained in:
MerryMage 2020-06-20 20:08:11 +01:00
parent b0beecdd41
commit 715db8381f
5 changed files with 57 additions and 1 deletions
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13
src/frontend/A32/decoder/asimd.h
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@ -40,10 +40,23 @@ std::vector<ASIMDMatcher<V>> GetASIMDDecodeTable() {
const std::set<std::string> comes_first{
"VBIC, VMOV, VMVN, VORR (immediate)"
};
const std::set<std::string> comes_last{
"VMLA (scalar)",
"VMLAL (scalar)",
"VQDMLAL/VQDMLSL",
"VMUL (scalar)",
"VMULL (scalar)",
"VQDMULL",
"VQDMULH",
"VQRDMULH",
};
std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) {
return comes_first.count(matcher.GetName()) > 0;
});
std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) {
return comes_last.count(matcher.GetName()) == 0;
});
return table;
}

3
src/frontend/A32/decoder/asimd.inc
View file

@ -50,10 +50,11 @@ INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd111
INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD
// Two registers and a scalar
INST(arm_UDF, "UNALLOCATED", "1111001-1-11-------------1-0----") // ASIMD
//INST(asimd_VMLA_scalar, "VMLA (scalar)", "1111001U1-BB--------0x0x-1-0----") // ASIMD
//INST(asimd_VMLAL_scalar, "VMLAL (scalar)", "1111001U1-BB--------0x10-1-0----") // ASIMD
//INST(asimd_VQDMLAL, "VQDMLAL/VQDMLSL", "111100101-BB--------0x11-1-0----") // ASIMD
//INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001U1-BB--------100x-1-0----") // ASIMD
INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001Q1Dzznnnndddd100FN1M0mmmm") // ASIMD
//INST(asimd_VMULL_scalar, "VMULL (scalar)", "1111001U1-BB--------1010-1-0----") // ASIMD
//INST(asimd_VQDMULL, "VQDMULL", "111100101-BB--------1011-1-0----") // ASIMD
//INST(asimd_VQDMULH, "VQDMULH", "1111001U1-BB--------1100-1-0----") // ASIMD