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A64: Implement UADDLP

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This commit is contained in:
MerryMage 2018-07-15 18:26:54 +01:00
parent 5563bbbd79
commit 70ff2d73b5
6 changed files with 104 additions and 8 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -614,7 +614,7 @@ INST(FABS_2, "FABS (vector)", "0Q001
//INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
//INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
//INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
//INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")

19
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -365,6 +365,25 @@ bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
IR::U128 result = ir.VectorPairedAddUnsignedWiden(esize, operand);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed);
}