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Merge pull request #562 from emuplz/a64_ic_instructions

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A64 IC Instructions
This commit is contained in:
merry 2021-02-17 21:51:58 +00:00 • committed by GitHub
commit 6f54c9d0b6
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GPG key ID: 4AEE18F83AFDEB23
12 changed files with 101 additions and 14 deletions
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5
src/frontend/A64/decoder/a64.inc
View file

@ -108,6 +108,11 @@ INST(DC_CVAU, "DC CVAU", "11010
INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt")
INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt")
// SYS: Instruction Cache
INST(IC_IALLU, "IC IALLU", "11010101000010000111010100011111")
INST(IC_IALLUIS, "IC IALLUIS", "11010101000010000111000100011111")
INST(IC_IVAU, "IC IVAU", "110101010000101101110101001ttttt")
// Unconditional branch (Register)
INST(BLR, "BLR", "1101011000111111000000nnnnn00000")
INST(BR, "BR", "1101011000011111000000nnnnn00000")

4
src/frontend/A64/ir_emitter.cpp
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@ -56,6 +56,10 @@ void IREmitter::DataCacheOperationRaised(DataCacheOperation op, const IR::U64& v
Inst(Opcode::A64DataCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
}
void IREmitter::InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value) {
Inst(Opcode::A64InstructionCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
}
void IREmitter::DataSynchronizationBarrier() {
Inst(Opcode::A64DataSynchronizationBarrier);
}

1
src/frontend/A64/ir_emitter.h
View file

@ -42,6 +42,7 @@ public:
void CallSupervisor(u32 imm);
void ExceptionRaised(Exception exception);
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
void InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value);
void DataSynchronizationBarrier();
void DataMemoryBarrier();
void InstructionSynchronizationBarrier();

5
src/frontend/A64/translate/impl/impl.h
View file

@ -174,6 +174,11 @@ struct TranslatorVisitor final {
bool DC_CVAP(Reg Rt);
bool DC_CIVAC(Reg Rt);
// SYS: Instruction Cache
bool IC_IALLU();
bool IC_IALLUIS();
bool IC_IVAU(Reg Rt);
// Unconditional branch (Register)
bool BR(Reg Rn);
bool BRA(bool Z, bool M, Reg Rn, Reg Rm);

25
src/frontend/A64/translate/impl/sys_ic.cpp Normal file
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@ -0,0 +1,25 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage
* SPDX-License-Identifier: 0BSD
*/
#include "frontend/A64/translate/impl/impl.h"
namespace Dynarmic::A64 {
bool TranslatorVisitor::IC_IALLU() {
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoU, ir.Imm64(0));
return true;
}
bool TranslatorVisitor::IC_IALLUIS() {
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoUInnerSharable, ir.Imm64(0));
return true;
}
bool TranslatorVisitor::IC_IVAU(Reg Rt) {
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateByVAToPoU, X(64, Rt));
return true;
}
} // namespace Dynarmic::A64

25
src/frontend/ir/microinstruction.cpp
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@ -520,18 +520,19 @@ bool Inst::IsSetCheckBitOperation() const {
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64DataCacheOperationRaised ||
IsSetCheckBitOperation() ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
return op == Opcode::PushRSB ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64InstructionCacheOperationRaised ||
IsSetCheckBitOperation() ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction();
}

1
src/frontend/ir/opcodes.inc
View file

@ -69,6 +69,7 @@ A64OPC(SetPC, Void, U64
A64OPC(CallSupervisor, Void, U32 )
A64OPC(ExceptionRaised, Void, U64, U64 )
A64OPC(DataCacheOperationRaised, Void, U64, U64 )
A64OPC(InstructionCacheOperationRaised, Void, U64, U64 )
A64OPC(DataSynchronizationBarrier, Void, )
A64OPC(DataMemoryBarrier, Void, )
A64OPC(InstructionSynchronizationBarrier, Void, )