emit_x64_vector: Ensure FPSR.QC is set even if output is invalidated

This commit is contained in:
Merry 2022-07-20 19:38:41 +01:00
parent 34cb465fc7
commit 6bcc424e1a
3 changed files with 67 additions and 47 deletions

View file

@ -1179,3 +1179,23 @@ TEST_CASE("A64: Memory access (fastmem)", "[a64]") {
jit.Run();
REQUIRE(strncmp(backing_memory + 0x100, backing_memory + 0x1F0, 23) == 0);
}
TEST_CASE("A64: SQRDMULH QC flag when output invalidated", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x0fbcd38b); // SQRDMULH.2S V11, V28, V28[1]
env.code_mem.emplace_back(0x7ef0f8eb); // FMINP.2D D11, V7
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(7, {0xb1b5'd0b1'4e54'e281, 0xb4cb'4fec'8563'1032});
jit.SetVector(28, {0x8000'0000'0000'0000, 0x0000'0000'0000'0000});
jit.SetFpcr(0x05400000);
env.ticks_left = 3;
jit.Run();
REQUIRE(jit.GetFpsr() == 0x08000000);
REQUIRE(jit.GetVector(11) == Vector{0xb4cb'4fec'8563'1032, 0x0000'0000'0000'0000});
}

View file

@ -211,7 +211,7 @@ static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv
fmt::print("{:3s}: {:016x}\n", A64::RegToString(static_cast<A64::Reg>(i)), regs[i]);
}
for (size_t i = 0; i < vecs.size(); ++i) {
fmt::print("{:3s}: {}{}\n", A64::VecToString(static_cast<A64::Vec>(i)), vecs[i][1], vecs[i][0]);
fmt::print("{:3s}: {:016x}{:016x}\n", A64::VecToString(static_cast<A64::Vec>(i)), vecs[i][1], vecs[i][0]);
}
fmt::print("sp : {:016x}\n", initial_sp);
fmt::print("pc : {:016x}\n", instructions_start);