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General: Correct typos is code comments

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Lioncash 2019-05-24 01:37:03 -04:00 • committed by MerryMage
parent 6187de7ca7
commit 6b9bf7868a
13 changed files with 16 additions and 16 deletions
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2
src/frontend/A32/translate/impl/vfp.cpp
View file

@ -44,7 +44,7 @@ bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, E
// The VFP register file is divided into banks each containing:
// * eight single-precision registers, or
// * four double-precision reigsters.
// * four double-precision registers.
// VFP vector instructions access these registers in a circular manner.
const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg {
const auto reg_number = static_cast<size_t>(reg);

2
src/frontend/A32/translate/translate_thumb.cpp
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@ -134,4 +134,4 @@ bool ThumbTranslatorVisitor::RaiseException(Exception exception) {
return false;
}
} // namepsace Dynarmic::A32
} // namespace Dynarmic::A32

4
src/frontend/A64/decoder/a64.inc
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@ -101,7 +101,7 @@ INST(DC_CVAU, "DC CVAU", "11010
INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt")
INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt")
// Unconditonal branch (Register)
// Unconditional branch (Register)
INST(BLR, "BLR", "1101011000111111000000nnnnn00000")
INST(BR, "BR", "1101011000011111000000nnnnn00000")
//INST(DRPS, "DRPS", "11010110101111110000001111100000")
@ -112,7 +112,7 @@ INST(RET, "RET", "11010
//INST(ERETA, "ERETAA, ERETAB", "110101101001111100001M1111111111") // ARMv8.3
//INST(RETA, "RETAA, RETAB", "110101100101111100001M1111111111") // ARMv8.3
// Unconditonal branch (immediate)
// Unconditional branch (immediate)
INST(B_uncond, "B", "000101iiiiiiiiiiiiiiiiiiiiiiiiii")
INST(BL, "BL", "100101iiiiiiiiiiiiiiiiiiiiiiiiii")

4
src/frontend/A64/translate/impl/impl.h
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@ -176,7 +176,7 @@ struct TranslatorVisitor final {
bool DC_CVAP(Reg Rt);
bool DC_CIVAC(Reg Rt);
// Unconditonal branch (Register)
// Unconditional branch (Register)
bool BR(Reg Rn);
bool BRA(bool Z, bool M, Reg Rn, Reg Rm);
bool BLR(Reg Rn);
@ -187,7 +187,7 @@ struct TranslatorVisitor final {
bool ERETA(bool M);
bool DRPS();
// Unconditonal branch (immediate)
// Unconditional branch (immediate)
bool B_uncond(Imm<26> imm26);
bool BL(Imm<26> imm26);

2
src/frontend/imm.h
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@ -143,7 +143,7 @@ bool operator>=(Imm<bit_size> a, u32 b) {
}
/**
* Concatentate immediates together.
* Concatenate immediates together.
* Left to right corresponds to most significant imm to least significant imm.
* This is equivalent to a:b:...:z in ASL.
*/

2
src/frontend/ir/basic_block.h
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@ -112,7 +112,7 @@ public:
LocationDescriptor ConditionFailedLocation() const;
/// Sets the location of the block to execute if the predicated condition fails.
void SetConditionFailedLocation(LocationDescriptor fail_location);
/// Determines whether or not a prediated condition failure block is present.
/// Determines whether or not a predicated condition failure block is present.
bool HasConditionFailedLocation() const;
/// Gets a mutable reference to the condition failed cycle count.

2
src/frontend/ir/microinstruction.h
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@ -109,7 +109,7 @@ public:
/// Pseudo-instructions depend on their parent instructions for their semantics.
bool IsAPseudoOperation() const;
/// Determins whether or not this instruction supports the GetNZCVFromOp pseudo-operation.
/// Determines whether or not this instruction supports the GetNZCVFromOp pseudo-operation.
bool MayGetNZCVFromOp() const;
/// Determines if all arguments of this instruction are immediates.