Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-04 05:34:42 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

jit_state: Hide cpsr implementation

Browse source
This commit is contained in:
MerryMage 2017-12-02 13:55:04 +00:00
parent a4e85ad565
commit 6adc554b53
8 changed files with 87 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

16
tests/arm/fuzz_arm.cpp
View file

@ -115,7 +115,7 @@ static void InterpreterFallback(u32 pc, Dynarmic::Jit* jit, void*) {
jit->Regs() = interp_state.Reg;
jit->ExtRegs() = interp_state.ExtReg;
jit->Cpsr() = interp_state.Cpsr;
jit->SetCpsr(interp_state.Cpsr);
jit->SetFpscr(interp_state.VFP[VFP_FPSCR]);
}
@ -233,7 +233,7 @@ void FuzzJitArm(const size_t instruction_count, const size_t instructions_to_exe
interp.ExtReg = initial_extregs;
interp.VFP[VFP_FPSCR] = initial_fpscr;
jit.Reset();
jit.Cpsr() = initial_cpsr;
jit.SetCpsr(initial_cpsr);
jit.Regs() = initial_regs;
jit.ExtRegs() = initial_extregs;
jit.SetFpscr(initial_fpscr);
@ -369,7 +369,7 @@ TEST_CASE( "arm: Optimization Failure (Randomized test case)", "[arm]" ) {
0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5,
0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0
};
jit.Cpsr() = 0x000001d0; // User-mode
jit.SetCpsr(0x000001d0); // User-mode
jit.Run(6);
@ -407,7 +407,7 @@ TEST_CASE( "arm: shsax r11, sp, r9 (Edge-case)", "[arm]" ) {
0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded,
0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000
};
jit.Cpsr() = 0x000001d0; // User-mode
jit.SetCpsr(0x000001d0); // User-mode
jit.Run(2);
@ -443,7 +443,7 @@ TEST_CASE( "arm: uasx (Edge-case)", "[arm]" ) {
jit.Regs()[4] = 0x8ed38f4c;
jit.Regs()[5] = 0x0000261d;
jit.Regs()[15] = 0x00000000;
jit.Cpsr() = 0x000001d0; // User-mode
jit.SetCpsr(0x000001d0); // User-mode
jit.Run(2);
@ -472,7 +472,7 @@ static void RunVfpTests(u32 instr, std::vector<VfpTest> tests) {
for (const auto& test : tests) {
jit.Regs()[15] = 0;
jit.Cpsr() = 0x000001d0;
jit.SetCpsr(0x000001d0);
jit.ExtRegs()[4] = test.a;
jit.ExtRegs()[6] = test.b;
jit.SetFpscr(test.initial_fpscr);
@ -1106,7 +1106,7 @@ TEST_CASE( "SMUAD", "[JitX64]" ) {
0, 0, 0, 0,
0, 0, 0, 0,
};
jit.Cpsr() = 0x000001d0; // User-mode
jit.SetCpsr(0x000001d0); // User-mode
jit.Run(6);
@ -1225,7 +1225,7 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm]") {
code_mem[3] = 0xeafffffe; // b +#0 (infinite loop)
jit.Regs() = {};
jit.Cpsr() = 0x000001d0; // User-mode
jit.SetCpsr(0x000001d0); // User-mode
jit.Run(4);

4
tests/arm/fuzz_thumb.cpp
View file

@ -107,7 +107,7 @@ static void InterpreterFallback(u32 pc, Dynarmic::Jit* jit, void*) {
interp_state.Reg[15] &= T ? 0xFFFFFFFE : 0xFFFFFFFC;
jit->Regs() = interp_state.Reg;
jit->Cpsr() = interp_state.Cpsr;
jit->SetCpsr(interp_state.Cpsr);
}
static void Fail() {
@ -204,7 +204,7 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e
interp.Cpsr = 0x000001F0;
interp.Reg = initial_regs;
jit.Cpsr() = 0x000001F0;
jit.SetCpsr(0x000001F0);
jit.Regs() = initial_regs;
std::generate_n(code_mem.begin(), instruction_count, instruction_generator);

16
tests/arm/test_thumb_instructions.cpp
View file

@ -43,7 +43,7 @@ static void InterpreterFallback(u32 pc, Dynarmic::Jit* jit, void*) {
InterpreterMainLoop(&interp_state);
jit->Regs() = interp_state.Reg;
jit->Cpsr() = interp_state.Cpsr;
jit->SetCpsr(interp_state.Cpsr);
}
static void AddTicks(u64) {}
@ -66,7 +66,7 @@ TEST_CASE( "thumb: lsls r0, r1, #2", "[thumb]" ) {
jit.Regs()[0] = 1;
jit.Regs()[1] = 2;
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -85,7 +85,7 @@ TEST_CASE( "thumb: lsls r0, r1, #31", "[thumb]" ) {
jit.Regs()[0] = 1;
jit.Regs()[1] = 0xFFFFFFFF;
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -103,7 +103,7 @@ TEST_CASE( "thumb: revsh r4, r3", "[thumb]" ) {
jit.Regs()[3] = 0x12345678;
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -121,7 +121,7 @@ TEST_CASE( "thumb: ldr r3, [r3, #28]", "[thumb]" ) {
jit.Regs()[3] = 0x12345678;
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -137,7 +137,7 @@ TEST_CASE( "thumb: blx +#67712", "[thumb]" ) {
code_mem[2] = 0xE7FE; // b +#0
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -153,7 +153,7 @@ TEST_CASE( "thumb: bl +#234584", "[thumb]" ) {
code_mem[2] = 0xE7FE; // b +#0
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);
@ -169,7 +169,7 @@ TEST_CASE( "thumb: bl -#42", "[thumb]" ) {
code_mem[2] = 0xE7FE; // b +#0
jit.Regs()[15] = 0; // PC = 0
jit.Cpsr() = 0x00000030; // Thumb, User-mode
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Run(1);