Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-06 22:48:25 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A64: Implement SVC

Browse source
This commit is contained in:
MerryMage 2018-01-08 22:03:03 +00:00
parent e5ace37560
commit 68391b0a05
9 changed files with 37 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.h
View file

@ -62,7 +62,7 @@ std::vector<Matcher<V>> GetDecodeTable() {
INST(&V::B_cond, "B.cond", "01010100iiiiiiiiiiiiiiiiiii0cccc"),
// Exception generation
//INST(&V::SVC, "SVC", "11010100000iiiiiiiiiiiiiiii00001"),
INST(&V::SVC, "SVC", "11010100000iiiiiiiiiiiiiiii00001"),
//INST(&V::HVC, "HVC", "11010100000iiiiiiiiiiiiiiii00010"),
//INST(&V::SMC, "SMC", "11010100000iiiiiiiiiiiiiiii00011"),
//INST(&V::BRK, "BRK", "11010100001iiiiiiiiiiiiiiii00000"),

4
src/frontend/A64/ir_emitter.cpp
View file

@ -34,6 +34,10 @@ void IREmitter::SetNZCV(const IR::NZCV& nzcv) {
Inst(Opcode::A64SetNZCV, nzcv);
}
void IREmitter::CallSupervisor(u32 imm) {
Inst(Opcode::A64CallSupervisor, Imm32(imm));
}
IR::U32 IREmitter::GetW(Reg reg) {
if (reg == Reg::ZR)
return Imm32(0);

2
src/frontend/A64/ir_emitter.h
View file

@ -35,6 +35,8 @@ public:
IR::U1 GetCFlag();
void SetNZCV(const IR::NZCV& nzcv);
void CallSupervisor(u32 imm);
IR::U32 GetW(Reg source_reg);
IR::U64 GetX(Reg source_reg);
IR::U64 GetSP();