Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-02 04:34:43 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Implement some simple IR optimizations (get/set eliminiation and DCE)

Browse source
This commit is contained in:
MerryMage 2016-07-21 21:48:45 +01:00
parent 90d317b868
commit 5fbfc6c155
16 changed files with 544 additions and 300 deletions
Download patch file Download diff file Expand all files Collapse all files

202
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -17,91 +17,11 @@ namespace Arm {
class DisassemblerVisitor {
public:
const char* CondStr(Cond cond) {
switch (cond) {
case Cond::EQ:
return "eq";
case Cond::NE:
return "ne";
case Cond::CS:
return "cs";
case Cond::CC:
return "cc";
case Cond::MI:
return "mi";
case Cond::PL:
return "pl";
case Cond::VS:
return "vs";
case Cond::VC:
return "vc";
case Cond::HI:
return "hi";
case Cond::LS:
return "ls";
case Cond::GE:
return "ge";
case Cond::LT:
return "lt";
case Cond::GT:
return "gt";
case Cond::LE:
return "le";
case Cond::AL:
return "";
case Cond::NV:
break;
}
assert(false);
return "<internal error>";
}
template<typename T>
const char* SignStr(T value) {
return value >= 0 ? "+" : "-";
}
const char* RegStr(Reg reg) {
switch (reg) {
case Reg::R0:
return "r0";
case Reg::R1:
return "r1";
case Reg::R2:
return "r2";
case Reg::R3:
return "r3";
case Reg::R4:
return "r4";
case Reg::R5:
return "r5";
case Reg::R6:
return "r6";
case Reg::R7:
return "r7";
case Reg::R8:
return "r8";
case Reg::R9:
return "r9";
case Reg::R10:
return "r10";
case Reg::R11:
return "r11";
case Reg::R12:
return "r12";
case Reg::R13:
return "sp";
case Reg::R14:
return "lr";
case Reg::R15:
return "pc";
case Reg::INVALID_REG:
break;
}
assert(false);
return "<internal error>";
}
u32 rotr(u32 x, int shift) {
shift &= 31;
if (!shift) return x;
@ -134,13 +54,13 @@ public:
std::string RsrStr(Reg s, ShiftType shift, Reg m) {
switch (shift){
case ShiftType::LSL:
return Common::StringFromFormat("%s, LSL %s", RegStr(m), RegStr(s));
return Common::StringFromFormat("%s, LSL %s", RegToString(m), RegToString(s));
case ShiftType::LSR:
return Common::StringFromFormat("%s, LSR %s", RegStr(m), RegStr(s));
return Common::StringFromFormat("%s, LSR %s", RegToString(m), RegToString(s));
case ShiftType::ASR:
return Common::StringFromFormat("%s, ASR %s", RegStr(m), RegStr(s));
return Common::StringFromFormat("%s, ASR %s", RegToString(m), RegToString(s));
case ShiftType::ROR:
return Common::StringFromFormat("%s, ROR %s", RegStr(m), RegStr(s));
return Common::StringFromFormat("%s, ROR %s", RegToString(m), RegToString(s));
}
assert(false);
return "<internal error>";
@ -149,24 +69,24 @@ public:
// Branch instructions
std::string arm_B(Cond cond, Imm24 imm24) {
s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8;
return Common::StringFromFormat("b%s %s#%i", CondStr(cond), SignStr(offset), abs(offset));
return Common::StringFromFormat("b%s %s#%i", CondToString(cond), SignStr(offset), abs(offset));
}
std::string arm_BL(Cond cond, Imm24 imm24) {
s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8;
return Common::StringFromFormat("bl%s %s#%i", CondStr(cond), SignStr(offset), abs(offset));
return Common::StringFromFormat("bl%s %s#%i", CondToString(cond), SignStr(offset), abs(offset));
}
std::string arm_BLX_imm(bool H, Imm24 imm24) {
s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8 + (H ? 2 : 0);
return Common::StringFromFormat("blx %s#%i", SignStr(offset), abs(offset));
}
std::string arm_BLX_reg(Cond cond, Reg m) {
return Common::StringFromFormat("blx%s %s", CondStr(cond), RegStr(m));
return Common::StringFromFormat("blx%s %s", CondToString(cond), RegToString(m));
}
std::string arm_BX(Cond cond, Reg m) {
return Common::StringFromFormat("bx%s %s", CondStr(cond), RegStr(m));
return Common::StringFromFormat("bx%s %s", CondToString(cond), RegToString(m));
}
std::string arm_BXJ(Cond cond, Reg m) {
return Common::StringFromFormat("bxj%s %s", CondStr(cond), RegStr(m));
return Common::StringFromFormat("bxj%s %s", CondToString(cond), RegToString(m));
}
// Coprocessor instructions
@ -180,154 +100,154 @@ public:
// Data processing instructions
std::string arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("adc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("adc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("add%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("add%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("add%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("add%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("and%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("and%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("and%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("and%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("bic%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("bic%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
return Common::StringFromFormat("cmn%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("cmn%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("cmn%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("cmn%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("cmn%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("cmn%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
return Common::StringFromFormat("cmp%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("cmp%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("cmp%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("cmp%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("cmp%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("cmp%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("eor%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("eor%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("mov%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("mov%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8));
}
std::string arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("mov%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("mov%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("mov%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("mov%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str());
}
std::string arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("mvn%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("mvn%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8));
}
std::string arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("mvn%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("mvn%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("mvn%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("mvn%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str());
}
std::string arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("orr%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("orr%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("sub%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("sub%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
return Common::StringFromFormat("teq%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("teq%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("teq%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("teq%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("teq%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("teq%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str());
}
std::string arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
return Common::StringFromFormat("tst%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
return Common::StringFromFormat("tst%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
}
std::string arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
return Common::StringFromFormat("tst%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
return Common::StringFromFormat("tst%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str());
}
std::string arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
return Common::StringFromFormat("tst%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
return Common::StringFromFormat("tst%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str());
}
// Exception generation instructions
std::string arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) { return "ice"; }
std::string arm_SVC(Cond cond, Imm24 imm24) {
return Common::StringFromFormat("svc%s #%u", CondStr(cond), imm24);
return Common::StringFromFormat("svc%s #%u", CondToString(cond), imm24);
}
std::string arm_UDF() {
return Common::StringFromFormat("udf");
@ -406,13 +326,13 @@ public:
// Reversal instructions
std::string arm_REV(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("rev%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
return Common::StringFromFormat("rev%s %s, %s", CondToString(cond), RegToString(d), RegToString(m));
}
std::string arm_REV16(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("rev16%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
return Common::StringFromFormat("rev16%s %s, %s", CondToString(cond), RegToString(d), RegToString(m));
}
std::string arm_REVSH(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("revsh%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
return Common::StringFromFormat("revsh%s %s, %s", CondToString(cond), RegToString(d), RegToString(m));
}
// Saturation instructions

202
src/frontend/disassembler/disassembler_thumb.cpp
View file

@ -17,91 +17,11 @@ namespace Arm {
class DisassemblerVisitor {
public:
const char* CondStr(Cond cond) {
switch (cond) {
case Cond::EQ:
return "eq";
case Cond::NE:
return "ne";
case Cond::CS:
return "cs";
case Cond::CC:
return "cc";
case Cond::MI:
return "mi";
case Cond::PL:
return "pl";
case Cond::VS:
return "vs";
case Cond::VC:
return "vc";
case Cond::HI:
return "hi";
case Cond::LS:
return "ls";
case Cond::GE:
return "ge";
case Cond::LT:
return "lt";
case Cond::GT:
return "gt";
case Cond::LE:
return "le";
case Cond::AL:
return "";
case Cond::NV:
break;
}
assert(false);
return "<internal error>";
}
template<typename T>
const char* SignStr(T value) {
return value >= 0 ? "+" : "-";
}
const char* RegStr(Reg reg) {
switch (reg) {
case Reg::R0:
return "r0";
case Reg::R1:
return "r1";
case Reg::R2:
return "r2";
case Reg::R3:
return "r3";
case Reg::R4:
return "r4";
case Reg::R5:
return "r5";
case Reg::R6:
return "r6";
case Reg::R7:
return "r7";
case Reg::R8:
return "r8";
case Reg::R9:
return "r9";
case Reg::R10:
return "r10";
case Reg::R11:
return "r11";
case Reg::R12:
return "r12";
case Reg::R13:
return "sp";
case Reg::R14:
return "lr";
case Reg::R15:
return "pc";
case Reg::INVALID_REG:
break;
}
assert(false);
return "<internal error>";
}
std::string RegListStr(RegList reg_list) {
std::string ret = "";
bool first_reg = true;
@ -109,7 +29,7 @@ public:
if (Common::Bit(i, reg_list)) {
if (!first_reg)
ret += ", ";
ret += RegStr(static_cast<Reg>(i));
ret += RegToString(static_cast<Reg>(i));
first_reg = false;
}
}
@ -117,210 +37,210 @@ public:
}
std::string thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("lsls %s, %s, #%u", RegStr(d), RegStr(m), imm5);
return Common::StringFromFormat("lsls %s, %s, #%u", RegToString(d), RegToString(m), imm5);
}
std::string thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("lsrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
return Common::StringFromFormat("lsrs %s, %s, #%u", RegToString(d), RegToString(m), imm5);
}
std::string thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("asrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
return Common::StringFromFormat("asrs %s, %s, #%u", RegToString(d), RegToString(m), imm5);
}
std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
return Common::StringFromFormat("adds %s, %s, %s", RegToString(d), RegToString(n), RegToString(m));
}
std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) {
return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
return Common::StringFromFormat("subs %s, %s, %s", RegToString(d), RegToString(n), RegToString(m));
}
std::string thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
return Common::StringFromFormat("adds %s, %s, #%u", RegToString(d), RegToString(n), imm3);
}
std::string thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3);
return Common::StringFromFormat("subs %s, %s, #%u", RegToString(d), RegToString(n), imm3);
}
std::string thumb16_MOV_imm(Reg d, Imm8 imm8) {
return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8);
return Common::StringFromFormat("movs %s, #%u", RegToString(d), imm8);
}
std::string thumb16_CMP_imm(Reg n, Imm8 imm8) {
return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8);
return Common::StringFromFormat("cmp %s, #%u", RegToString(n), imm8);
}
std::string thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) {
return Common::StringFromFormat("adds %s, #%u", RegStr(d_n), imm8);
return Common::StringFromFormat("adds %s, #%u", RegToString(d_n), imm8);
}
std::string thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) {
return Common::StringFromFormat("subs %s, #%u", RegStr(d_n), imm8);
return Common::StringFromFormat("subs %s, #%u", RegToString(d_n), imm8);
}
std::string thumb16_AND_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("ands %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_EOR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("eors %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("eors %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_LSL_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("lsls %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_LSR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("lsrs %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("lsrs %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_ASR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("asrs %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("asrs %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_ADC_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("adcs %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("adcs %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_SBC_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("sbcs %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("sbcs %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_ROR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("rors %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("rors %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_TST_reg(Reg m, Reg n) {
return Common::StringFromFormat("tst %s, %s", RegStr(n), RegStr(m));
return Common::StringFromFormat("tst %s, %s", RegToString(n), RegToString(m));
}
std::string thumb16_RSB_imm(Reg n, Reg d) {
// Pre-UAL syntax: NEGS <Rd>, <Rn>
return Common::StringFromFormat("rsbs %s, %s, #0", RegStr(d), RegStr(n));
return Common::StringFromFormat("rsbs %s, %s, #0", RegToString(d), RegToString(n));
}
std::string thumb16_CMP_reg_t1(Reg m, Reg n) {
return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m));
return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m));
}
std::string thumb16_CMN_reg(Reg m, Reg n) {
return Common::StringFromFormat("cmn %s, %s", RegStr(n), RegStr(m));
return Common::StringFromFormat("cmn %s, %s", RegToString(n), RegToString(m));
}
std::string thumb16_ORR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("orrs %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("orrs %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_BIC_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("bics %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("bics %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_MVN_reg(Reg m, Reg d) {
return Common::StringFromFormat("mvns %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("mvns %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));
return Common::StringFromFormat("add %s, %s", RegToString(d_n), RegToString(m));
}
std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
Reg n = n_hi ? (n_lo + 8) : n_lo;
return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m));
return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m));
}
std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
Reg d = d_hi ? (d_lo + 8) : d_lo;
return Common::StringFromFormat("mov %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("mov %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_LDR_literal(Reg t, Imm8 imm8) {
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("ldr %s, [pc, #%u]", RegStr(t), imm32);
return Common::StringFromFormat("ldr %s, [pc, #%u]", RegToString(t), imm32);
}
std::string thumb16_STR_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("str %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("str %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("strh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("strh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("strb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("strb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("ldrsb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("ldrsb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("ldr %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("ldr %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("ldrh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("ldrh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("ldrb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("ldrb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) {
return Common::StringFromFormat("ldrsh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
return Common::StringFromFormat("ldrsh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
}
std::string thumb16_STR_imm_t1(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5 << 2;
return Common::StringFromFormat("str %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("str %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5 << 2;
return Common::StringFromFormat("ldr %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("ldr %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_STRB_imm(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5;
return Common::StringFromFormat("strb %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("strb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_LDRB_imm(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5;
return Common::StringFromFormat("ldrb %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("ldrb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_STRH_imm(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5 << 1;
return Common::StringFromFormat("strh %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("strh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_LDRH_imm(Imm5 imm5, Reg n, Reg t) {
u32 imm32 = imm5 << 1;
return Common::StringFromFormat("ldrh %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
return Common::StringFromFormat("ldrh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32);
}
std::string thumb16_STR_imm_t2(Reg t, Imm5 imm5) {
u32 imm32 = imm5 << 2;
return Common::StringFromFormat("str %s, [sp, #%u]", RegStr(t), imm32);
return Common::StringFromFormat("str %s, [sp, #%u]", RegToString(t), imm32);
}
std::string thumb16_LDR_imm_t2(Reg t, Imm5 imm5) {
u32 imm32 = imm5 << 2;
return Common::StringFromFormat("ldr %s, [sp, #%u]", RegStr(t), imm32);
return Common::StringFromFormat("ldr %s, [sp, #%u]", RegToString(t), imm32);
}
std::string thumb16_ADR(Reg d, Imm8 imm8) {
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("adr %s, +#%u", RegStr(d), imm32);
return Common::StringFromFormat("adr %s, +#%u", RegToString(d), imm32);
}
std::string thumb16_ADD_sp_t1(Reg d, Imm8 imm8) {
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("add %s, sp, #%u", RegStr(d), imm32);
return Common::StringFromFormat("add %s, sp, #%u", RegToString(d), imm32);
}
std::string thumb16_ADD_sp_t2(Imm7 imm7) {
@ -334,19 +254,19 @@ public:
}
std::string thumb16_SXTH(Reg m, Reg d) {
return Common::StringFromFormat("sxth %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("sxth %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_SXTB(Reg m, Reg d) {
return Common::StringFromFormat("sxtb %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("sxtb %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_UXTH(Reg m, Reg d) {
return Common::StringFromFormat("uxth %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("uxth %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_UXTB(Reg m, Reg d) {
return Common::StringFromFormat("uxtb %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("uxtb %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_PUSH(bool M, RegList reg_list) {
@ -364,32 +284,32 @@ public:
}
std::string thumb16_REV(Reg m, Reg d) {
return Common::StringFromFormat("rev %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("rev %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_REV16(Reg m, Reg d) {
return Common::StringFromFormat("rev16 %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("rev16 %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_REVSH(Reg m, Reg d) {
return Common::StringFromFormat("revsh %s, %s", RegStr(d), RegStr(m));
return Common::StringFromFormat("revsh %s, %s", RegToString(d), RegToString(m));
}
std::string thumb16_STMIA(Reg n, RegList reg_list) {
return Common::StringFromFormat("stm %s!, %s", RegStr(n), RegListStr(reg_list).c_str());
return Common::StringFromFormat("stm %s!, %s", RegToString(n), RegListStr(reg_list).c_str());
}
std::string thumb16_LDMIA(Reg n, RegList reg_list) {
bool write_back = !Dynarmic::Common::Bit(static_cast<size_t>(n), reg_list);
return Common::StringFromFormat("ldm %s%s, %s", RegStr(n), write_back ? "!" : "", RegListStr(reg_list).c_str());
return Common::StringFromFormat("ldm %s%s, %s", RegToString(n), write_back ? "!" : "", RegListStr(reg_list).c_str());
}
std::string thumb16_BX(Reg m) {
return Common::StringFromFormat("bx %s", RegStr(m));
return Common::StringFromFormat("bx %s", RegToString(m));
}
std::string thumb16_BLX_reg(Reg m) {
return Common::StringFromFormat("blx %s", RegStr(m));
return Common::StringFromFormat("blx %s", RegToString(m));
}
std::string thumb16_UDF() {
@ -402,7 +322,7 @@ public:
std::string thumb16_B_t1(Cond cond, Imm8 imm8) {
s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4;
return Common::StringFromFormat("b%s %s#%u", CondStr(cond), SignStr(imm32), abs(imm32));
return Common::StringFromFormat("b%s %s#%u", CondToString(cond), SignStr(imm32), abs(imm32));
}
std::string thumb16_B_t2(Imm11 imm11) {