Implement CLZ

Includes tests
This commit is contained in:
MerryMage 2016-12-04 22:56:33 +00:00
parent 1a1646d962
commit 5c1aab1666
8 changed files with 64 additions and 2 deletions

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@ -386,6 +386,10 @@ Value IREmitter::PackedSaturatedSubS16(const Value& a, const Value& b) {
return Inst(Opcode::PackedSaturatedSubS16, {a, b});
}
Value IREmitter::CountLeadingZeros(const Value& a) {
return Inst(Opcode::CountLeadingZeros, {a});
}
Value IREmitter::TransferToFP32(const Value& a) {
return Inst(Opcode::TransferToFP32, {a});
}

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@ -142,6 +142,7 @@ public:
Value PackedSaturatedAddS16(const Value& a, const Value& b);
Value PackedSaturatedSubU16(const Value& a, const Value& b);
Value PackedSaturatedSubS16(const Value& a, const Value& b);
Value CountLeadingZeros(const Value& a);
Value TransferToFP32(const Value& a);
Value TransferToFP64(const Value& a);

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@ -87,6 +87,7 @@ OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
OPCODE(CountLeadingZeros, T::U32, T::U32 )
// Floating-point operations
OPCODE(TransferToFP32, T::F32, T::U32 )

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@ -0,0 +1,22 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2016 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "translate_arm.h"
namespace Dynarmic {
namespace Arm {
bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
if (d == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
}
return true;
}
} // namespace Arm
} // namespace Dynarmic

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@ -209,7 +209,7 @@ struct ArmTranslatorVisitor final {
bool arm_STM_usr();
// Miscellaneous instructions
bool arm_CLZ(Cond cond, Reg d, Reg m) { return InterpretThisInstruction(); }
bool arm_CLZ(Cond cond, Reg d, Reg m);
bool arm_NOP() { return true; }
bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);