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Implement CLZ
Includes tests
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1a1646d962
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8 changed files with 64 additions and 2 deletions
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@ -386,6 +386,10 @@ Value IREmitter::PackedSaturatedSubS16(const Value& a, const Value& b) {
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return Inst(Opcode::PackedSaturatedSubS16, {a, b});
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}
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Value IREmitter::CountLeadingZeros(const Value& a) {
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return Inst(Opcode::CountLeadingZeros, {a});
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}
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Value IREmitter::TransferToFP32(const Value& a) {
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return Inst(Opcode::TransferToFP32, {a});
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}
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@ -142,6 +142,7 @@ public:
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Value PackedSaturatedAddS16(const Value& a, const Value& b);
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Value PackedSaturatedSubU16(const Value& a, const Value& b);
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Value PackedSaturatedSubS16(const Value& a, const Value& b);
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Value CountLeadingZeros(const Value& a);
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Value TransferToFP32(const Value& a);
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Value TransferToFP64(const Value& a);
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@ -87,6 +87,7 @@ OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32
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OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
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OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
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OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
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OPCODE(CountLeadingZeros, T::U32, T::U32 )
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// Floating-point operations
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OPCODE(TransferToFP32, T::F32, T::U32 )
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22
src/frontend/translate/translate_arm/misc.cpp
Normal file
22
src/frontend/translate/translate_arm/misc.cpp
Normal file
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@ -0,0 +1,22 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
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}
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return true;
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}
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} // namespace Arm
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} // namespace Dynarmic
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@ -209,7 +209,7 @@ struct ArmTranslatorVisitor final {
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bool arm_STM_usr();
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// Miscellaneous instructions
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bool arm_CLZ(Cond cond, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_CLZ(Cond cond, Reg d, Reg m);
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bool arm_NOP() { return true; }
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bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
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