mirror of
https://git.suyu.dev/suyu/dynarmic.git
synced 2026-01-06 06:28:13 +01:00
More Speed
This commit is contained in:
MerryMage
parent
5fbfc6c155
commit
51448aa06d
16 changed files with 1066 additions and 955 deletions
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@ -52,94 +52,69 @@ const char* GetNameOf(Opcode op) {
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// Value class member definitions
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void Value::ReplaceUsesWith(ValuePtr replacement) {
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while (!uses.empty()) {
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auto use = uses.front();
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use.use_owner.lock()->ReplaceUseOfXWithY(use.value.lock(), replacement);
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}
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}
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std::vector<ValuePtr> Value::GetUses() const {
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std::vector<ValuePtr> result(uses.size());
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std::transform(uses.begin(), uses.end(), result.begin(), [](const auto& use){ return use.use_owner.lock(); });
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return result;
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}
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void Value::AddUse(ValuePtr owner) {
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// There can be multiple uses from the same owner.
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uses.push_back({ shared_from_this(), owner });
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}
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void Value::RemoveUse(ValuePtr owner) {
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// Remove only one use.
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auto iter = std::find_if(uses.begin(), uses.end(), [&owner](auto use) { return use.use_owner.lock() == owner; });
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ASSERT_MSG(iter != uses.end(), "RemoveUse without associated AddUse. Bug in use management code.");
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uses.erase(iter);
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}
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void Value::ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) {
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// This should never be called. Use management is incorrect if this is ever called.
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ASSERT_MSG(false, "This Value type doesn't use any values. Bug in use management code.");
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}
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void Value::AssertValid() {
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ASSERT(std::all_of(uses.begin(), uses.end(), [](const auto& use) { return !use.use_owner.expired(); }));
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Type Value::GetType() const {
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return IsImmediate() ? type : inner.inst->GetType();
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}
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// Inst class member definitions
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Inst::Inst(Opcode op_) : Value(op_) {
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args.resize(GetNumArgsOf(op));
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Value Inst::GetArg(size_t index) const {
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DEBUG_ASSERT(index < GetNumArgsOf(op));
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DEBUG_ASSERT(!args[index].IsEmpty());
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return args[index];
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}
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void Inst::SetArg(size_t index, ValuePtr value) {
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auto this_ = shared_from_this();
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void Inst::SetArg(size_t index, Value value) {
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DEBUG_ASSERT(index < GetNumArgsOf(op));
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DEBUG_ASSERT(value.GetType() == GetArgTypeOf(op, index));
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if (auto prev_value = args.at(index).lock()) {
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prev_value->RemoveUse(this_);
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if (!args[index].IsImmediate()) {
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UndoUse(args[index]);
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}
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if (!value.IsImmediate()) {
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Use(value);
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}
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ASSERT(value->GetType() == GetArgTypeOf(op, index));
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args.at(index) = value;
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value->AddUse(this_);
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}
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ValuePtr Inst::GetArg(size_t index) const {
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ASSERT_MSG(!args.at(index).expired(), "This should never happen. All Values should be owned by a MicroBlock.");
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return args.at(index).lock();
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args[index] = value;
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}
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void Inst::Invalidate() {
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AssertValid();
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ASSERT(!HasUses());
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auto this_ = shared_from_this();
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for (auto& arg : args) {
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arg.lock()->RemoveUse(this_);
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}
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}
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void Inst::AssertValid() {
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ASSERT(std::all_of(args.begin(), args.end(), [](const auto& arg) { return !arg.expired(); }));
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Value::AssertValid();
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}
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void Inst::ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) {
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bool has_use = false;
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auto this_ = shared_from_this();
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// Note that there may be multiple uses of x.
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for (auto& arg : args) {
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if (arg.lock() == x) {
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arg = y;
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has_use = true;
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x->RemoveUse(this_);
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y->AddUse(this_);
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for (auto& value : args) {
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if (!value.IsImmediate()) {
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UndoUse(value);
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}
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}
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}
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ASSERT_MSG(has_use, "This Inst doesn't have x. Bug in use management code.");
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void Inst::Use(Value& value) {
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value.GetInst()->use_count++;
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switch (op){
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case Opcode::GetCarryFromOp:
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value.GetInst()->carry_inst = this;
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break;
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case Opcode::GetOverflowFromOp:
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value.GetInst()->overflow_inst = this;
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break;
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default:
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break;
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}
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}
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void Inst::UndoUse(Value& value) {
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value.GetInst()->use_count--;
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switch (op){
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case Opcode::GetCarryFromOp:
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value.GetInst()->carry_inst = nullptr;
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break;
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case Opcode::GetOverflowFromOp:
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value.GetInst()->overflow_inst = nullptr;
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break;
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default:
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break;
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}
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}
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std::string DumpBlock(const IR::Block& block) {
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@ -160,65 +135,48 @@ std::string DumpBlock(const IR::Block& block) {
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}
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ret += "\n";
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std::map<IR::Value*, size_t> value_to_index;
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std::map<const IR::Inst*, size_t> inst_to_index;
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size_t index = 0;
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const auto arg_to_string = [&value_to_index](IR::ValuePtr arg) -> std::string {
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if (!arg) {
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const auto arg_to_string = [&inst_to_index](const IR::Value& arg) -> std::string {
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if (arg.IsEmpty()) {
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return "<null>";
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} else if (!arg.IsImmediate()) {
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return Common::StringFromFormat("%%%zu", inst_to_index.at(arg.GetInst()));
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}
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switch (arg->GetOpcode()) {
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case Opcode::ImmU1: {
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auto inst = reinterpret_cast<ImmU1*>(arg.get());
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return Common::StringFromFormat("#%s", inst->value ? "1" : "0");
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}
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case Opcode::ImmU8: {
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auto inst = reinterpret_cast<ImmU8*>(arg.get());
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return Common::StringFromFormat("#%u", inst->value);
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}
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case Opcode::ImmU32: {
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auto inst = reinterpret_cast<ImmU32*>(arg.get());
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return Common::StringFromFormat("#%#x", inst->value);
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}
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case Opcode::ImmRegRef: {
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auto inst = reinterpret_cast<ImmRegRef*>(arg.get());
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return Arm::RegToString(inst->value);
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}
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default: {
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return Common::StringFromFormat("%%%zu", value_to_index.at(arg.get()));
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}
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switch (arg.GetType()) {
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case Type::U1:
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return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0");
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case Type::U8:
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return Common::StringFromFormat("#%u", arg.GetU8());
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case Type::U32:
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return Common::StringFromFormat("#%#x", arg.GetU32());
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case Type::RegRef:
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return Arm::RegToString(arg.GetRegRef());
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default:
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return "<unknown immediate type>";
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}
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};
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for (const auto& inst_ptr : block.instructions) {
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const Opcode op = inst_ptr->GetOpcode();
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switch (op) {
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case Opcode::ImmU1:
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case Opcode::ImmU8:
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case Opcode::ImmU32:
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case Opcode::ImmRegRef:
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break;
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default: {
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if (GetTypeOf(op) != Type::Void) {
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ret += Common::StringFromFormat("%%%-5zu = ", index);
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} else {
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ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces
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}
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for (auto inst = block.instructions.begin(); inst != block.instructions.end(); ++inst) {
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const Opcode op = inst->GetOpcode();
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ret += GetNameOf(op);
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const size_t arg_count = GetNumArgsOf(op);
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const auto inst = reinterpret_cast<Inst*>(inst_ptr.get());
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for (size_t arg_index = 0; arg_index < arg_count; arg_index++) {
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ret += arg_index != 0 ? ", " : " ";
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ret += arg_to_string(inst->GetArg(arg_index));
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}
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ret += "\n";
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value_to_index[inst_ptr.get()] = index++;
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break;
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}
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if (GetTypeOf(op) != Type::Void) {
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ret += Common::StringFromFormat("%%%-5zu = ", index);
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} else {
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ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces
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}
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ret += GetNameOf(op);
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const size_t arg_count = GetNumArgsOf(op);
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for (size_t arg_index = 0; arg_index < arg_count; arg_index++) {
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ret += arg_index != 0 ? ", " : " ";
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ret += arg_to_string(inst->GetArg(arg_index));
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}
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ret += "\n";
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inst_to_index.at(&*inst) = index++;
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}
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return ret;
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@ -10,9 +10,12 @@
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#include <memory>
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#include <vector>
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#include <boost/variant.hpp>
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#include <boost/pool/pool.hpp>
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#include <boost/intrusive/list.hpp>
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#include <boost/optional.hpp>
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#include <boost/variant.hpp>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "frontend/arm_types.h"
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#include "frontend/ir/opcodes.h"
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@ -47,22 +50,91 @@ const char* GetNameOf(Opcode op);
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// Type declarations
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/// Base class for microinstructions to derive from.
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/**
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* A representation of a microinstruction. A single ARM/Thumb instruction may be
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* converted into zero or more microinstructions.
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*/
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class Value;
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using ValuePtr = std::shared_ptr<Value>;
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using ValueWeakPtr = std::weak_ptr<Value>;
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struct Value;
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class Inst;
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class Value : public std::enable_shared_from_this<Value> {
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struct Value final {
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public:
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virtual ~Value() = default;
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Value() : type(Type::Void) {}
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bool HasUses() const { return !uses.empty(); }
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bool HasOneUse() const { return uses.size() == 1; }
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bool HasManyUses() const { return uses.size() > 1; }
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explicit Value(Inst* value) : type(Type::Opaque) {
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inner.inst = value;
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}
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/// Replace all uses of this Value with `replacement`.
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void ReplaceUsesWith(ValuePtr replacement);
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explicit Value(Arm::Reg value) : type(Type::RegRef) {
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inner.imm_regref = value;
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}
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explicit Value(bool value) : type(Type::U1) {
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inner.imm_u1 = value;
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}
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explicit Value(u8 value) : type(Type::U8) {
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inner.imm_u8 = value;
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}
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explicit Value(u32 value) : type(Type::U32) {
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inner.imm_u32 = value;
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}
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bool IsEmpty() const {
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return type == Type::Void;
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}
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bool IsImmediate() const {
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return type != Type::Opaque;
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}
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Type GetType() const;
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Inst* GetInst() const {
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DEBUG_ASSERT(type == Type::Opaque);
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return inner.inst;
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}
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Arm::Reg GetRegRef() const {
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DEBUG_ASSERT(type == Type::RegRef);
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return inner.imm_regref;
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}
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bool GetU1() const {
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DEBUG_ASSERT(type == Type::U1);
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return inner.imm_u1;
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}
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u8 GetU8() const {
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DEBUG_ASSERT(type == Type::U8);
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return inner.imm_u8;
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}
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u32 GetU32() const {
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DEBUG_ASSERT(type == Type::U32);
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return inner.imm_u32;
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}
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private:
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Type type;
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union {
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Inst* inst; // type == Type::Opaque
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Arm::Reg imm_regref;
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bool imm_u1;
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u8 imm_u8;
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u32 imm_u32;
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} inner;
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};
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using InstListLinkMode = boost::intrusive::link_mode<boost::intrusive::normal_link>;
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class Inst final : public boost::intrusive::list_base_hook<InstListLinkMode> {
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public:
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Inst(Opcode op) : op(op) {}
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bool HasUses() const { return use_count > 0; }
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/// Get the microop this microinstruction represents.
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Opcode GetOpcode() const { return op; }
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@ -70,99 +142,22 @@ public:
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Type GetType() const { return GetTypeOf(op); }
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/// Get the number of arguments this instruction has.
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size_t NumArgs() const { return GetNumArgsOf(op); }
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/// Get the number of uses this instruction has.
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size_t NumUses() const { return uses.size(); }
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std::vector<ValuePtr> GetUses() const;
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Value GetArg(size_t index) const;
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void SetArg(size_t index, Value value);
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/// Prepare this Value for removal from the instruction stream.
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virtual void Invalidate() {}
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/// Assert that this Value is valid.
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virtual void AssertValid();
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void Invalidate();
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intptr_t GetTag() const { return tag; }
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void SetTag(intptr_t tag_) { tag = tag_; }
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protected:
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friend class Inst;
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explicit Value(Opcode op_) : op(op_) {}
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void AddUse(ValuePtr owner);
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void RemoveUse(ValuePtr owner);
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virtual void ReplaceUseOfXWithY(ValuePtr x, ValuePtr y);
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size_t use_count = 0;
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Inst* carry_inst = nullptr;
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Inst* overflow_inst = nullptr;
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private:
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void Use(Value& value);
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void UndoUse(Value& value);
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Opcode op;
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struct Use {
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/// The instruction which is being used.
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ValueWeakPtr value;
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/// The instruction which is using `value`.
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ValueWeakPtr use_owner;
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};
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std::list<Use> uses;
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intptr_t tag = 0;
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};
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/// Representation of a u1 immediate.
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class ImmU1 final : public Value {
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public:
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explicit ImmU1(bool value_) : Value(Opcode::ImmU1), value(value_) {}
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~ImmU1() override = default;
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const bool value; ///< Literal value to load
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};
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/// Representation of a u8 immediate.
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class ImmU8 final : public Value {
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public:
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explicit ImmU8(u8 value_) : Value(Opcode::ImmU8), value(value_) {}
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~ImmU8() override = default;
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const u8 value; ///< Literal value to load
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};
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/// Representation of a u32 immediate.
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class ImmU32 final : public Value {
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public:
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explicit ImmU32(u32 value_) : Value(Opcode::ImmU32), value(value_) {}
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~ImmU32() override = default;
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const u32 value; ///< Literal value to load
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};
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/// Representation of a GPR reference.
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class ImmRegRef final : public Value {
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public:
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explicit ImmRegRef(Arm::Reg value_) : Value(Opcode::ImmRegRef), value(value_) {}
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~ImmRegRef() override = default;
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const Arm::Reg value; ///< Literal value to load
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};
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/**
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* A representation of a microinstruction. A single ARM/Thumb instruction may be
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* converted into zero or more microinstructions.
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*/
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class Inst final : public Value {
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public:
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explicit Inst(Opcode op);
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~Inst() override = default;
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/// Set argument number `index` to `value`.
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void SetArg(size_t index, ValuePtr value);
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/// Get argument number `index`.
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ValuePtr GetArg(size_t index) const;
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void Invalidate() override;
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void AssertValid() override;
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protected:
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void ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) override;
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private:
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std::vector<ValueWeakPtr> args;
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std::array<Value, 3> args;
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};
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namespace Term {
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@ -261,7 +256,9 @@ public:
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boost::optional<Arm::LocationDescriptor> cond_failed = {};
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/// List of instructions in this block.
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std::list<ValuePtr> instructions;
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boost::intrusive::list<Inst, InstListLinkMode> instructions;
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/// Memory pool for instruction list
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std::unique_ptr<boost::pool<>> instruction_alloc_pool = std::make_unique<boost::pool<>>(sizeof(Inst));
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/// Terminal instruction of this block.
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Terminal terminal = Term::Invalid{};
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@ -24,138 +24,132 @@ u32 IREmitter::AlignPC(size_t alignment) {
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return static_cast<u32>(pc - pc % alignment);
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}
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IR::ValuePtr IREmitter::Imm1(bool value) {
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auto imm1 = std::make_shared<IR::ImmU1>(value);
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AddToBlock(imm1);
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return imm1;
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IR::Value IREmitter::Imm1(bool imm1) {
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return IR::Value(imm1);
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}
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|
||||
IR::ValuePtr IREmitter::Imm8(u8 i) {
|
||||
auto imm8 = std::make_shared<IR::ImmU8>(i);
|
||||
AddToBlock(imm8);
|
||||
return imm8;
|
||||
IR::Value IREmitter::Imm8(u8 imm8) {
|
||||
return IR::Value(imm8);
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Imm32(u32 i) {
|
||||
auto imm32 = std::make_shared<IR::ImmU32>(i);
|
||||
AddToBlock(imm32);
|
||||
return imm32;
|
||||
IR::Value IREmitter::Imm32(u32 imm32) {
|
||||
return IR::Value(imm32);
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::GetRegister(Reg reg) {
|
||||
IR::Value IREmitter::GetRegister(Reg reg) {
|
||||
if (reg == Reg::PC) {
|
||||
return Imm32(PC());
|
||||
}
|
||||
return Inst(IR::Opcode::GetRegister, { RegRef(reg) });
|
||||
return Inst(IR::Opcode::GetRegister, { IR::Value(reg) });
|
||||
}
|
||||
|
||||
void IREmitter::SetRegister(const Reg reg, IR::ValuePtr value) {
|
||||
void IREmitter::SetRegister(const Reg reg, const IR::Value& value) {
|
||||
ASSERT(reg != Reg::PC);
|
||||
Inst(IR::Opcode::SetRegister, { RegRef(reg), value });
|
||||
Inst(IR::Opcode::SetRegister, { IR::Value(reg), value });
|
||||
}
|
||||
|
||||
void IREmitter::ALUWritePC(IR::ValuePtr value) {
|
||||
void IREmitter::ALUWritePC(const IR::Value& value) {
|
||||
// This behaviour is ARM version-dependent.
|
||||
// The below implementation is for ARMv6k
|
||||
BranchWritePC(value);
|
||||
}
|
||||
|
||||
void IREmitter::BranchWritePC(IR::ValuePtr value) {
|
||||
void IREmitter::BranchWritePC(const IR::Value& value) {
|
||||
if (!current_location.TFlag) {
|
||||
auto new_pc = And(value, Imm32(0xFFFFFFFC));
|
||||
Inst(IR::Opcode::SetRegister, { RegRef(Reg::PC), new_pc });
|
||||
Inst(IR::Opcode::SetRegister, { IR::Value(Reg::PC), new_pc });
|
||||
} else {
|
||||
auto new_pc = And(value, Imm32(0xFFFFFFFE));
|
||||
Inst(IR::Opcode::SetRegister, { RegRef(Reg::PC), new_pc });
|
||||
Inst(IR::Opcode::SetRegister, { IR::Value(Reg::PC), new_pc });
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::BXWritePC(IR::ValuePtr value) {
|
||||
void IREmitter::BXWritePC(const IR::Value& value) {
|
||||
Inst(IR::Opcode::BXWritePC, {value});
|
||||
}
|
||||
|
||||
void IREmitter::LoadWritePC(IR::ValuePtr value) {
|
||||
void IREmitter::LoadWritePC(const IR::Value& value) {
|
||||
// This behaviour is ARM version-dependent.
|
||||
// The below implementation is for ARMv6k
|
||||
BXWritePC(value);
|
||||
}
|
||||
|
||||
void IREmitter::CallSupervisor(IR::ValuePtr value) {
|
||||
void IREmitter::CallSupervisor(const IR::Value& value) {
|
||||
Inst(IR::Opcode::CallSupervisor, {value});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::GetCFlag() {
|
||||
IR::Value IREmitter::GetCFlag() {
|
||||
return Inst(IR::Opcode::GetCFlag, {});
|
||||
}
|
||||
|
||||
void IREmitter::SetNFlag(IR::ValuePtr value) {
|
||||
void IREmitter::SetNFlag(const IR::Value& value) {
|
||||
Inst(IR::Opcode::SetNFlag, {value});
|
||||
}
|
||||
|
||||
void IREmitter::SetZFlag(IR::ValuePtr value) {
|
||||
void IREmitter::SetZFlag(const IR::Value& value) {
|
||||
Inst(IR::Opcode::SetZFlag, {value});
|
||||
}
|
||||
|
||||
void IREmitter::SetCFlag(IR::ValuePtr value) {
|
||||
void IREmitter::SetCFlag(const IR::Value& value) {
|
||||
Inst(IR::Opcode::SetCFlag, {value});
|
||||
}
|
||||
|
||||
void IREmitter::SetVFlag(IR::ValuePtr value) {
|
||||
void IREmitter::SetVFlag(const IR::Value& value) {
|
||||
Inst(IR::Opcode::SetVFlag, {value});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::LeastSignificantHalf(IR::ValuePtr value) {
|
||||
IR::Value IREmitter::LeastSignificantHalf(const IR::Value& value) {
|
||||
return Inst(IR::Opcode::LeastSignificantHalf, {value});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::LeastSignificantByte(IR::ValuePtr value) {
|
||||
IR::Value IREmitter::LeastSignificantByte(const IR::Value& value) {
|
||||
return Inst(IR::Opcode::LeastSignificantByte, {value});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::MostSignificantBit(IR::ValuePtr value) {
|
||||
IR::Value IREmitter::MostSignificantBit(const IR::Value& value) {
|
||||
return Inst(IR::Opcode::MostSignificantBit, {value});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::IsZero(IR::ValuePtr value) {
|
||||
IR::Value IREmitter::IsZero(const IR::Value& value) {
|
||||
return Inst(IR::Opcode::IsZero, {value});
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarry IREmitter::LogicalShiftLeft(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarry IREmitter::LogicalShiftLeft(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in) {
|
||||
auto result = Inst(IR::Opcode::LogicalShiftLeft, {value_in, shift_amount, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
return {result, carry_out};
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarry IREmitter::LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarry IREmitter::LogicalShiftRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in) {
|
||||
auto result = Inst(IR::Opcode::LogicalShiftRight, {value_in, shift_amount, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
return {result, carry_out};
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarry IREmitter::ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarry IREmitter::ArithmeticShiftRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in) {
|
||||
auto result = Inst(IR::Opcode::ArithmeticShiftRight, {value_in, shift_amount, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
return {result, carry_out};
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarry IREmitter::RotateRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarry IREmitter::RotateRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in) {
|
||||
auto result = Inst(IR::Opcode::RotateRight, {value_in, shift_amount, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
return {result, carry_out};
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(const IR::Value& a, const IR::Value& b, const IR::Value& carry_in) {
|
||||
auto result = Inst(IR::Opcode::AddWithCarry, {a, b, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
auto overflow = Inst(IR::Opcode::GetOverflowFromOp, {result});
|
||||
return {result, carry_out, overflow};
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Add(IR::ValuePtr a, IR::ValuePtr b) {
|
||||
IR::Value IREmitter::Add(const IR::Value& a, const IR::Value& b) {
|
||||
return Inst(IR::Opcode::AddWithCarry, {a, b, Imm1(0)});
|
||||
}
|
||||
|
||||
IREmitter::ResultAndCarryAndOverflow IREmitter::SubWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in) {
|
||||
IREmitter::ResultAndCarryAndOverflow IREmitter::SubWithCarry(const IR::Value& a, const IR::Value& b, const IR::Value& carry_in) {
|
||||
// This is equivalent to AddWithCarry(a, Not(b), carry_in).
|
||||
auto result = Inst(IR::Opcode::SubWithCarry, {a, b, carry_in});
|
||||
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
|
||||
|
|
@ -163,96 +157,102 @@ IREmitter::ResultAndCarryAndOverflow IREmitter::SubWithCarry(IR::ValuePtr a, IR:
|
|||
return {result, carry_out, overflow};
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Sub(IR::ValuePtr a, IR::ValuePtr b) {
|
||||
IR::Value IREmitter::Sub(const IR::Value& a, const IR::Value& b) {
|
||||
return Inst(IR::Opcode::SubWithCarry, {a, b, Imm1(1)});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::And(IR::ValuePtr a, IR::ValuePtr b) {
|
||||
IR::Value IREmitter::And(const IR::Value& a, const IR::Value& b) {
|
||||
return Inst(IR::Opcode::And, {a, b});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Eor(IR::ValuePtr a, IR::ValuePtr b) {
|
||||
IR::Value IREmitter::Eor(const IR::Value& a, const IR::Value& b) {
|
||||
return Inst(IR::Opcode::Eor, {a, b});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Or(IR::ValuePtr a, IR::ValuePtr b) {
|
||||
IR::Value IREmitter::Or(const IR::Value& a, const IR::Value& b) {
|
||||
return Inst(IR::Opcode::Or, {a, b});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Not(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::Not(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::Not, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::SignExtendHalfToWord(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::SignExtendHalfToWord(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::SignExtendHalfToWord, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::SignExtendByteToWord(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::SignExtendByteToWord(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::SignExtendByteToWord, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ZeroExtendHalfToWord(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::ZeroExtendHalfToWord(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::ZeroExtendHalfToWord, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ZeroExtendByteToWord(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::ZeroExtendByteToWord(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::ZeroExtendByteToWord, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ByteReverseWord(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::ByteReverseWord(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::ByteReverseWord, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ByteReverseHalf(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::ByteReverseHalf(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::ByteReverseHalf, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ByteReverseDual(IR::ValuePtr a) {
|
||||
IR::Value IREmitter::ByteReverseDual(const IR::Value& a) {
|
||||
return Inst(IR::Opcode::ByteReverseDual, {a});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ReadMemory8(IR::ValuePtr vaddr) {
|
||||
IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) {
|
||||
return Inst(IR::Opcode::ReadMemory8, {vaddr});
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ReadMemory16(IR::ValuePtr vaddr) {
|
||||
IR::Value IREmitter::ReadMemory16(const IR::Value& vaddr) {
|
||||
auto value = Inst(IR::Opcode::ReadMemory16, {vaddr});
|
||||
return current_location.EFlag ? ByteReverseHalf(value) : value;
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ReadMemory32(IR::ValuePtr vaddr) {
|
||||
IR::Value IREmitter::ReadMemory32(const IR::Value& vaddr) {
|
||||
auto value = Inst(IR::Opcode::ReadMemory32, {vaddr});
|
||||
return current_location.EFlag ? ByteReverseWord(value) : value;
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::ReadMemory64(IR::ValuePtr vaddr) {
|
||||
IR::Value IREmitter::ReadMemory64(const IR::Value& vaddr) {
|
||||
auto value = Inst(IR::Opcode::ReadMemory64, {vaddr});
|
||||
return current_location.EFlag ? ByteReverseDual(value) : value;
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory8(IR::ValuePtr vaddr, IR::ValuePtr value) {
|
||||
void IREmitter::WriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
|
||||
Inst(IR::Opcode::WriteMemory8, {vaddr, value});
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory16(IR::ValuePtr vaddr, IR::ValuePtr value) {
|
||||
void IREmitter::WriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
|
||||
if (current_location.EFlag) {
|
||||
value = ByteReverseHalf(value);
|
||||
auto v = ByteReverseHalf(value);
|
||||
Inst(IR::Opcode::WriteMemory16, {vaddr, v});
|
||||
} else {
|
||||
Inst(IR::Opcode::WriteMemory16, {vaddr, value});
|
||||
}
|
||||
Inst(IR::Opcode::WriteMemory16, {vaddr, value});
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory32(IR::ValuePtr vaddr, IR::ValuePtr value) {
|
||||
void IREmitter::WriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
|
||||
if (current_location.EFlag) {
|
||||
value = ByteReverseWord(value);
|
||||
auto v = ByteReverseWord(value);
|
||||
Inst(IR::Opcode::WriteMemory32, {vaddr, v});
|
||||
} else {
|
||||
Inst(IR::Opcode::WriteMemory32, {vaddr, value});
|
||||
}
|
||||
Inst(IR::Opcode::WriteMemory32, {vaddr, value});
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory64(IR::ValuePtr vaddr, IR::ValuePtr value) {
|
||||
void IREmitter::WriteMemory64(const IR::Value& vaddr, const IR::Value& value) {
|
||||
if (current_location.EFlag) {
|
||||
value = ByteReverseDual(value);
|
||||
auto v = ByteReverseDual(value);
|
||||
Inst(IR::Opcode::WriteMemory64, {vaddr, v});
|
||||
} else {
|
||||
Inst(IR::Opcode::WriteMemory64, {vaddr, value});
|
||||
}
|
||||
Inst(IR::Opcode::WriteMemory64, {vaddr, value});
|
||||
}
|
||||
|
||||
void IREmitter::SetTerm(const IR::Terminal& terminal) {
|
||||
|
|
@ -260,28 +260,18 @@ void IREmitter::SetTerm(const IR::Terminal& terminal) {
|
|||
block.terminal = terminal;
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::Inst(IR::Opcode op, std::initializer_list<IR::ValuePtr> args) {
|
||||
auto inst = std::make_shared<IR::Inst>(op);
|
||||
assert(args.size() == inst->NumArgs());
|
||||
IR::Value IREmitter::Inst(IR::Opcode op, std::initializer_list<IR::Value> args) {
|
||||
IR::Inst* inst = new(block.instruction_alloc_pool->malloc()) IR::Inst(op);
|
||||
DEBUG_ASSERT(args.size() == inst->NumArgs());
|
||||
|
||||
std::for_each(args.begin(), args.end(), [&inst, op, index = size_t(0)](const auto& v) mutable {
|
||||
assert(IR::GetArgTypeOf(op, index) == v->GetType());
|
||||
DEBUG_ASSERT(IR::GetArgTypeOf(op, index) == v.GetType());
|
||||
inst->SetArg(index, v);
|
||||
index++;
|
||||
});
|
||||
|
||||
AddToBlock(inst);
|
||||
return inst;
|
||||
}
|
||||
|
||||
IR::ValuePtr IREmitter::RegRef(Reg reg) {
|
||||
auto regref = std::make_shared<IR::ImmRegRef>(reg);
|
||||
AddToBlock(regref);
|
||||
return regref;
|
||||
}
|
||||
|
||||
void IREmitter::AddToBlock(IR::ValuePtr value) {
|
||||
block.instructions.emplace_back(value);
|
||||
block.instructions.push_back(*inst);
|
||||
return IR::Value(inst);
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
|
|
@ -21,79 +21,77 @@ public:
|
|||
LocationDescriptor current_location;
|
||||
|
||||
struct ResultAndCarry {
|
||||
IR::ValuePtr result;
|
||||
IR::ValuePtr carry;
|
||||
IR::Value result;
|
||||
IR::Value carry;
|
||||
};
|
||||
|
||||
struct ResultAndCarryAndOverflow {
|
||||
IR::ValuePtr result;
|
||||
IR::ValuePtr carry;
|
||||
IR::ValuePtr overflow;
|
||||
IR::Value result;
|
||||
IR::Value carry;
|
||||
IR::Value overflow;
|
||||
};
|
||||
|
||||
void Unimplemented();
|
||||
u32 PC();
|
||||
u32 AlignPC(size_t alignment);
|
||||
|
||||
IR::ValuePtr Imm1(bool value);
|
||||
IR::ValuePtr Imm8(u8 value);
|
||||
IR::ValuePtr Imm32(u32 value);
|
||||
IR::Value Imm1(bool value);
|
||||
IR::Value Imm8(u8 value);
|
||||
IR::Value Imm32(u32 value);
|
||||
|
||||
IR::ValuePtr GetRegister(Reg source_reg);
|
||||
void SetRegister(const Reg dest_reg, IR::ValuePtr value);
|
||||
IR::Value GetRegister(Reg source_reg);
|
||||
void SetRegister(const Reg dest_reg, const IR::Value& value);
|
||||
|
||||
void ALUWritePC(IR::ValuePtr value);
|
||||
void BranchWritePC(IR::ValuePtr value);
|
||||
void BXWritePC(IR::ValuePtr value);
|
||||
void LoadWritePC(IR::ValuePtr value);
|
||||
void CallSupervisor(IR::ValuePtr value);
|
||||
void ALUWritePC(const IR::Value& value);
|
||||
void BranchWritePC(const IR::Value& value);
|
||||
void BXWritePC(const IR::Value& value);
|
||||
void LoadWritePC(const IR::Value& value);
|
||||
void CallSupervisor(const IR::Value& value);
|
||||
|
||||
IR::ValuePtr GetCFlag();
|
||||
void SetNFlag(IR::ValuePtr value);
|
||||
void SetZFlag(IR::ValuePtr value);
|
||||
void SetCFlag(IR::ValuePtr value);
|
||||
void SetVFlag(IR::ValuePtr value);
|
||||
IR::Value GetCFlag();
|
||||
void SetNFlag(const IR::Value& value);
|
||||
void SetZFlag(const IR::Value& value);
|
||||
void SetCFlag(const IR::Value& value);
|
||||
void SetVFlag(const IR::Value& value);
|
||||
|
||||
IR::ValuePtr LeastSignificantHalf(IR::ValuePtr value);
|
||||
IR::ValuePtr LeastSignificantByte(IR::ValuePtr value);
|
||||
IR::ValuePtr MostSignificantBit(IR::ValuePtr value);
|
||||
IR::ValuePtr IsZero(IR::ValuePtr value);
|
||||
IR::Value LeastSignificantHalf(const IR::Value& value);
|
||||
IR::Value LeastSignificantByte(const IR::Value& value);
|
||||
IR::Value MostSignificantBit(const IR::Value& value);
|
||||
IR::Value IsZero(const IR::Value& value);
|
||||
|
||||
ResultAndCarry LogicalShiftLeft(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
|
||||
ResultAndCarry LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
|
||||
ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
|
||||
ResultAndCarry RotateRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
|
||||
ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
|
||||
IR::ValuePtr Add(IR::ValuePtr a, IR::ValuePtr b);
|
||||
ResultAndCarryAndOverflow SubWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
|
||||
IR::ValuePtr Sub(IR::ValuePtr a, IR::ValuePtr b);
|
||||
IR::ValuePtr And(IR::ValuePtr a, IR::ValuePtr b);
|
||||
IR::ValuePtr Eor(IR::ValuePtr a, IR::ValuePtr b);
|
||||
IR::ValuePtr Or(IR::ValuePtr a, IR::ValuePtr b);
|
||||
IR::ValuePtr Not(IR::ValuePtr a);
|
||||
IR::ValuePtr SignExtendHalfToWord(IR::ValuePtr a);
|
||||
IR::ValuePtr SignExtendByteToWord(IR::ValuePtr a);
|
||||
IR::ValuePtr ZeroExtendHalfToWord(IR::ValuePtr a);
|
||||
IR::ValuePtr ZeroExtendByteToWord(IR::ValuePtr a);
|
||||
IR::ValuePtr ByteReverseWord(IR::ValuePtr a);
|
||||
IR::ValuePtr ByteReverseHalf(IR::ValuePtr a);
|
||||
IR::ValuePtr ByteReverseDual(IR::ValuePtr a);
|
||||
ResultAndCarry LogicalShiftLeft(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in);
|
||||
ResultAndCarry LogicalShiftRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in);
|
||||
ResultAndCarry ArithmeticShiftRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in);
|
||||
ResultAndCarry RotateRight(const IR::Value& value_in, const IR::Value& shift_amount, const IR::Value& carry_in);
|
||||
ResultAndCarryAndOverflow AddWithCarry(const IR::Value& a, const IR::Value& b, const IR::Value& carry_in);
|
||||
IR::Value Add(const IR::Value& a, const IR::Value& b);
|
||||
ResultAndCarryAndOverflow SubWithCarry(const IR::Value& a, const IR::Value& b, const IR::Value& carry_in);
|
||||
IR::Value Sub(const IR::Value& a, const IR::Value& b);
|
||||
IR::Value And(const IR::Value& a, const IR::Value& b);
|
||||
IR::Value Eor(const IR::Value& a, const IR::Value& b);
|
||||
IR::Value Or(const IR::Value& a, const IR::Value& b);
|
||||
IR::Value Not(const IR::Value& a);
|
||||
IR::Value SignExtendHalfToWord(const IR::Value& a);
|
||||
IR::Value SignExtendByteToWord(const IR::Value& a);
|
||||
IR::Value ZeroExtendHalfToWord(const IR::Value& a);
|
||||
IR::Value ZeroExtendByteToWord(const IR::Value& a);
|
||||
IR::Value ByteReverseWord(const IR::Value& a);
|
||||
IR::Value ByteReverseHalf(const IR::Value& a);
|
||||
IR::Value ByteReverseDual(const IR::Value& a);
|
||||
|
||||
IR::ValuePtr ReadMemory8(IR::ValuePtr vaddr);
|
||||
IR::ValuePtr ReadMemory16(IR::ValuePtr vaddr);
|
||||
IR::ValuePtr ReadMemory32(IR::ValuePtr vaddr);
|
||||
IR::ValuePtr ReadMemory64(IR::ValuePtr vaddr);
|
||||
void WriteMemory8(IR::ValuePtr vaddr, IR::ValuePtr value);
|
||||
void WriteMemory16(IR::ValuePtr vaddr, IR::ValuePtr value);
|
||||
void WriteMemory32(IR::ValuePtr vaddr, IR::ValuePtr value);
|
||||
void WriteMemory64(IR::ValuePtr vaddr, IR::ValuePtr value);
|
||||
IR::Value ReadMemory8(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory16(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory32(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory64(const IR::Value& vaddr);
|
||||
void WriteMemory8(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory16(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory32(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory64(const IR::Value& vaddr, const IR::Value& value);
|
||||
|
||||
void SetTerm(const IR::Terminal& terminal);
|
||||
|
||||
private:
|
||||
IR::ValuePtr Inst(IR::Opcode op, std::initializer_list<IR::ValuePtr> args);
|
||||
IR::ValuePtr RegRef(Reg reg);
|
||||
void AddToBlock(IR::ValuePtr value);
|
||||
IR::Value Inst(IR::Opcode op, std::initializer_list<IR::Value> args);
|
||||
};
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
|
|
@ -1,11 +1,5 @@
|
|||
// opcode name, return type, arg1 type, arg2 type, arg3 type, ...
|
||||
|
||||
// Immediate values
|
||||
OPCODE(ImmU1, T::U1, )
|
||||
OPCODE(ImmU8, T::U8, )
|
||||
OPCODE(ImmU32, T::U32, )
|
||||
OPCODE(ImmRegRef, T::RegRef, )
|
||||
|
||||
// ARM Context getters/setters
|
||||
OPCODE(GetRegister, T::U32, T::RegRef )
|
||||
OPCODE(SetRegister, T::Void, T::RegRef, T::U32 )
|
||||
|
|
|
|||
|
|
@ -340,7 +340,7 @@ IR::Block TranslateArm(LocationDescriptor descriptor, MemoryRead32FuncType memor
|
|||
visitor.ir.block.cond_failed = { visitor.ir.current_location };
|
||||
}
|
||||
|
||||
return visitor.ir.block;
|
||||
return std::move(visitor.ir.block);
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
|
|
@ -888,7 +888,7 @@ IR::Block TranslateThumb(LocationDescriptor descriptor, MemoryRead32FuncType mem
|
|||
visitor.ir.block.cycle_count++;
|
||||
}
|
||||
|
||||
return visitor.ir.block;
|
||||
return std::move(visitor.ir.block);
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue