From 50bb31710472e19b4f35eb3127a1c07a62931a53 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 25 Apr 2017 13:45:31 +0100 Subject: [PATCH] parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15 --- src/frontend/translate/translate_arm/parallel.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/frontend/translate/translate_arm/parallel.cpp b/src/frontend/translate/translate_arm/parallel.cpp index 92cfc486..9fb5b781 100644 --- a/src/frontend/translate/translate_arm/parallel.cpp +++ b/src/frontend/translate/translate_arm/parallel.cpp @@ -205,6 +205,8 @@ bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) { } bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) + return UnpredictableInstruction(); if (ConditionPassed(cond)) { auto result = ir.PackedSaturatedAddU8(ir.GetRegister(n), ir.GetRegister(m)); ir.SetRegister(d, result); @@ -213,6 +215,8 @@ bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) { } bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) + return UnpredictableInstruction(); if (ConditionPassed(cond)) { auto result = ir.PackedSaturatedAddU16(ir.GetRegister(n), ir.GetRegister(m)); ir.SetRegister(d, result);