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IR: Implement FPVectorTo{Signed,Unsigned}Fixed

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This commit is contained in:
MerryMage 2018-07-26 12:08:56 +01:00
parent 8f75a1fe04
commit 507bcd8b8b
4 changed files with 99 additions and 7 deletions
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32
src/frontend/ir/ir_emitter.cpp
View file

@ -1822,6 +1822,14 @@ U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128&
return {};
}
U128 IREmitter::FPVectorS32ToSingle(const U128& a) {
return Inst<U128>(Opcode::FPVectorS32ToSingle, a);
}
U128 IREmitter::FPVectorS64ToDouble(const U128& a) {
return Inst<U128>(Opcode::FPVectorS64ToDouble, a);
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
@ -1833,12 +1841,28 @@ U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
return {};
}
U128 IREmitter::FPVectorS32ToSingle(const U128& a) {
return Inst<U128>(Opcode::FPVectorS32ToSingle, a);
U128 IREmitter::FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
ASSERT(fbits <= esize);
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorToSignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
case 64:
return Inst<U128>(Opcode::FPVectorToSignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorS64ToDouble(const U128& a) {
return Inst<U128>(Opcode::FPVectorS64ToDouble, a);
U128 IREmitter::FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
ASSERT(fbits <= esize);
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorToUnsignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
case 64:
return Inst<U128>(Opcode::FPVectorToUnsignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorU32ToSingle(const U128& a) {

4
src/frontend/ir/ir_emitter.h
View file

@ -312,9 +312,11 @@ public:
U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorS32ToSingle(const U128& a);
U128 FPVectorS64ToDouble(const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorU32ToSingle(const U128& a);
U128 FPVectorU64ToDouble(const U128& a);

8
src/frontend/ir/opcodes.inc
View file

@ -454,10 +454,10 @@ OPCODE(FPVectorMulAdd64, T::U128, T::U128,
OPCODE(FPVectorNeg16, T::U128, T::U128 )
OPCODE(FPVectorNeg32, T::U128, T::U128 )
OPCODE(FPVectorNeg64, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRecipEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRecipEstimate64, T::U128, T::U128 )
OPCODE(FPVectorRecipStepFused32, T::U128, T::U128, T::U128 )
@ -470,6 +470,10 @@ OPCODE(FPVectorS32ToSingle, T::U128, T::U128
OPCODE(FPVectorS64ToDouble, T::U128, T::U128 )
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorSub64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorToSignedFixed32, T::U128, T::U128, T::U8, T::U8 )
OPCODE(FPVectorToSignedFixed64, T::U128, T::U128, T::U8, T::U8 )
OPCODE(FPVectorToUnsignedFixed32, T::U128, T::U128, T::U8, T::U8 )
OPCODE(FPVectorToUnsignedFixed64, T::U128, T::U128, T::U8, T::U8 )
OPCODE(FPVectorU32ToSingle, T::U128, T::U128 )
OPCODE(FPVectorU64ToDouble, T::U128, T::U128 )