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https://git.suyu.dev/suyu/dynarmic.git
synced 2025-12-25 16:54:40 +01:00
RegAlloc: Allow allocation of XMM registers
This commit is contained in:
MerryMage
parent
864081d1a0
commit
4414ec5bc8
5 changed files with 218 additions and 131 deletions
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@ -21,13 +21,14 @@ static Gen::X64Reg HostLocToX64(HostLoc loc) {
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}
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static Gen::OpArg SpillToOpArg(HostLoc loc) {
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static_assert(std::is_same<decltype(JitState{}.Spill[0]), u64&>::value, "Spill must be u64");
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DEBUG_ASSERT(HostLocIsSpill(loc));
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size_t i = static_cast<size_t>(loc) - static_cast<size_t>(HostLoc::FirstSpill);
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return Gen::MDisp(Gen::R15, static_cast<int>(offsetof(JitState, Spill) + i * sizeof(u32)));
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return Gen::MDisp(Gen::R15, static_cast<int>(offsetof(JitState, Spill) + i * sizeof(u64)));
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}
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Gen::X64Reg RegAlloc::DefRegister(IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::DefRegister(IR::Inst* def_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocations(def_inst).empty(), "def_inst has already been defined");
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@ -38,13 +39,11 @@ Gen::X64Reg RegAlloc::DefRegister(IR::Inst* def_inst, std::initializer_list<Host
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}
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// Update state
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hostloc_state[static_cast<size_t>(location)] = HostLocState::Def;
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hostloc_to_inst[static_cast<size_t>(location)] = def_inst;
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LocInfo(location) = {def_inst, HostLocState::Def};
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return HostLocToX64(location);
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}
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Value use_value, IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseDefRegister(use_value.GetInst(), def_inst, desired_locations);
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}
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@ -52,19 +51,19 @@ Gen::X64Reg RegAlloc::UseDefRegister(IR::Value use_value, IR::Inst* def_inst, st
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return LoadImmediateIntoRegister(use_value, DefRegister(def_inst, desired_locations));
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}
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Inst* use_inst, IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Inst* use_inst, IR::Inst* def_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocations(def_inst).empty(), "def_inst has already been defined");
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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// TODO: Optimize the case when this is the last use_inst use.
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Gen::X64Reg use_reg = UseRegister(use_inst);
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Gen::X64Reg use_reg = UseRegister(use_inst, any_gpr);
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Gen::X64Reg def_reg = DefRegister(def_inst, desired_locations);
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code->MOV(32, Gen::R(def_reg), Gen::R(use_reg));
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code->MOV(64, Gen::R(def_reg), Gen::R(use_reg));
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return def_reg;
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}
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Gen::X64Reg RegAlloc::UseRegister(IR::Value use_value, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseRegister(IR::Value use_value, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseRegister(use_value.GetInst(), desired_locations);
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}
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@ -72,17 +71,18 @@ Gen::X64Reg RegAlloc::UseRegister(IR::Value use_value, std::initializer_list<Hos
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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HostLoc current_location = ValueLocations(use_inst).front();
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auto iter = std::find(desired_locations.begin(), desired_locations.end(), current_location);
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if (iter != desired_locations.end()) {
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle || hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Use);
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ASSERT(LocInfo(current_location).state == HostLocState::Idle ||
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LocInfo(current_location).state == HostLocState::Use);
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// Update state
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hostloc_state[static_cast<size_t>(current_location)] = HostLocState::Use;
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LocInfo(current_location).state = HostLocState::Use;
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DecrementRemainingUses(use_inst);
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return HostLocToX64(current_location);
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@ -95,18 +95,19 @@ Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, std::initializer_list<Host
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SpillRegister(new_location);
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}
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code->MOV(32, Gen::R(HostLocToX64(new_location)), SpillToOpArg(current_location));
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EmitMove(new_location, current_location);
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Use;
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std::swap(hostloc_to_inst[static_cast<size_t>(new_location)], hostloc_to_inst[static_cast<size_t>(current_location)]);
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LocInfo(new_location) = LocInfo(current_location);
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LocInfo(new_location).state = HostLocState::Use;
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LocInfo(current_location) = {};
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DecrementRemainingUses(use_inst);
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} else if (HostLocIsRegister(current_location)) {
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle);
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ASSERT(LocInfo(current_location).state == HostLocState::Idle);
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code->XCHG(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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EmitExchange(new_location, current_location);
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Use;
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std::swap(hostloc_to_inst[static_cast<size_t>(new_location)], hostloc_to_inst[static_cast<size_t>(current_location)]);
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std::swap(LocInfo(new_location), LocInfo(current_location));
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LocInfo(new_location).state = HostLocState::Use;
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DecrementRemainingUses(use_inst);
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} else {
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ASSERT_MSG(0, "Invalid current_location");
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@ -115,7 +116,7 @@ Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, std::initializer_list<Host
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return HostLocToX64(new_location);
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}
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value use_value, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value use_value, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseScratchRegister(use_value.GetInst(), desired_locations);
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}
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@ -123,7 +124,7 @@ Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value use_value, std::initializer_l
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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ASSERT_MSG(use_inst->use_count != 0, "use_inst ran out of uses. (Use-d an IR::Inst* too many times)");
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@ -136,23 +137,23 @@ Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, std::initializer_li
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SpillRegister(new_location);
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}
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code->MOV(32, Gen::R(HostLocToX64(new_location)), SpillToOpArg(current_location));
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EmitMove(new_location, current_location);
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Scratch;
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LocInfo(new_location).state = HostLocState::Scratch;
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DecrementRemainingUses(use_inst);
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} else if (HostLocIsRegister(current_location)) {
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle);
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ASSERT(LocInfo(current_location).state == HostLocState::Idle);
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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if (current_location != new_location) {
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code->MOV(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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EmitMove(new_location, current_location);
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}
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} else {
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code->MOV(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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EmitMove(new_location, current_location);
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}
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Scratch;
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LocInfo(new_location).state = HostLocState::Scratch;
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DecrementRemainingUses(use_inst);
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} else {
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ASSERT_MSG(0, "Invalid current_location");
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@ -161,8 +162,7 @@ Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, std::initializer_li
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return HostLocToX64(new_location);
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}
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Gen::X64Reg RegAlloc::ScratchRegister(std::initializer_list<HostLoc> desired_locations) {
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Gen::X64Reg RegAlloc::ScratchRegister(HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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HostLoc location = SelectARegister(desired_locations);
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@ -172,7 +172,7 @@ Gen::X64Reg RegAlloc::ScratchRegister(std::initializer_list<HostLoc> desired_loc
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}
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// Update state
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hostloc_state[static_cast<size_t>(location)] = HostLocState::Scratch;
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LocInfo(location).state = HostLocState::Scratch;
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return HostLocToX64(location);
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}
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@ -235,7 +235,7 @@ void RegAlloc::HostCall(IR::Inst* result_def, IR::Value arg0_use, IR::Value arg1
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code->MOV(64, Gen::R(Gen::RSP), Gen::MDisp(Gen::R15, offsetof(JitState, save_host_RSP)));
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}
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HostLoc RegAlloc::SelectARegister(std::initializer_list<HostLoc> desired_locations) const {
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HostLoc RegAlloc::SelectARegister(HostLocList desired_locations) const {
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std::vector<HostLoc> candidates = desired_locations;
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// Find all locations that have not been allocated..
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@ -259,32 +259,32 @@ std::vector<HostLoc> RegAlloc::ValueLocations(IR::Inst* value) const {
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std::vector<HostLoc> locations;
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for (size_t i = 0; i < HostLocCount; i++)
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if (hostloc_to_inst[i] == value)
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if (hostloc_info[i].value == value)
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locations.emplace_back(static_cast<HostLoc>(i));
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return locations;
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}
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bool RegAlloc::IsRegisterOccupied(HostLoc loc) const {
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return hostloc_to_inst.at(static_cast<size_t>(loc)) != nullptr;
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return GetLocInfo(loc).value != nullptr;
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}
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bool RegAlloc::IsRegisterAllocated(HostLoc loc) const {
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return hostloc_state.at(static_cast<size_t>(loc)) != HostLocState::Idle;
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return GetLocInfo(loc).state != HostLocState::Idle;
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}
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void RegAlloc::SpillRegister(HostLoc loc) {
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ASSERT_MSG(HostLocIsRegister(loc), "Only registers can be spilled");
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ASSERT_MSG(hostloc_state[static_cast<size_t>(loc)] == HostLocState::Idle, "Allocated registers cannot be spilled");
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ASSERT_MSG(LocInfo(loc).state == HostLocState::Idle, "Allocated registers cannot be spilled");
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ASSERT_MSG(IsRegisterOccupied(loc), "There is no need to spill unoccupied registers");
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ASSERT_MSG(!IsRegisterAllocated(loc), "Registers that have been allocated must not be spilt");
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HostLoc new_loc = FindFreeSpill();
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code->MOV(32, SpillToOpArg(new_loc), Gen::R(HostLocToX64(loc)));
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EmitMove(new_loc, loc);
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hostloc_to_inst[static_cast<size_t>(new_loc)] = hostloc_to_inst[static_cast<size_t>(loc)];
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hostloc_to_inst[static_cast<size_t>(loc)] = nullptr;
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LocInfo(new_loc).value = LocInfo(loc).value;
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LocInfo(loc).value = nullptr;
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}
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HostLoc RegAlloc::FindFreeSpill() const {
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@ -296,11 +296,11 @@ HostLoc RegAlloc::FindFreeSpill() const {
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}
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void RegAlloc::EndOfAllocScope() {
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hostloc_state.fill(HostLocState::Idle);
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for (auto& iter : hostloc_to_inst)
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if (iter && iter->use_count == 0)
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iter = nullptr;
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for (auto& iter : hostloc_info) {
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iter.state = HostLocState::Idle;
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if (iter.value && iter.value->use_count == 0)
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iter.value = nullptr;
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}
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}
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void RegAlloc::DecrementRemainingUses(IR::Inst* value) {
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@ -309,12 +309,53 @@ void RegAlloc::DecrementRemainingUses(IR::Inst* value) {
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}
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void RegAlloc::AssertNoMoreUses() {
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ASSERT(std::all_of(hostloc_to_inst.begin(), hostloc_to_inst.end(), [](const auto& inst){ return !inst; }));
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ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i){ return !i.value; }));
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}
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void RegAlloc::Reset() {
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hostloc_to_inst.fill(nullptr);
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hostloc_state.fill(HostLocState::Idle);
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hostloc_info.fill({});
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}
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void RegAlloc::EmitMove(HostLoc to, HostLoc from) {
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const auto& from_info = LocInfo(from);
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if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
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if (from_info.GetType() == IR::Type::F64) {
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code->MOVSD(HostLocToX64(to), SpillToOpArg(from));
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} else if (from_info.GetType() == IR::Type::F32) {
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code->MOVSS(HostLocToX64(to), SpillToOpArg(from));
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} else {
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ASSERT_MSG(false, "Tried to move a non-fp value into an XMM register");
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}
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} else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
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if (from_info.GetType() == IR::Type::F64) {
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code->MOVSD(SpillToOpArg(to), HostLocToX64(from));
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} else if (from_info.GetType() == IR::Type::F32) {
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code->MOVSS(SpillToOpArg(to), HostLocToX64(from));
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} else {
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ASSERT_MSG(false, "Tried to move a non-fp value into an XMM register");
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}
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} else if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
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code->MOVAPS(HostLocToX64(to), Gen::R(HostLocToX64(from)));
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} else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
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code->MOV(64, Gen::R(HostLocToX64(to)), SpillToOpArg(from));
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} else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
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code->MOV(64, SpillToOpArg(to), Gen::R(HostLocToX64(from)));
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} else if (HostLocIsGPR(to) && HostLocIsGPR(from)){
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code->MOV(64, Gen::R(HostLocToX64(to)), Gen::R(HostLocToX64(from)));
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} else {
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ASSERT_MSG(false, "Invalid RegAlloc::EmitMove");
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}
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}
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void RegAlloc::EmitExchange(HostLoc a, HostLoc b) {
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if (HostLocIsGPR(a) && HostLocIsGPR(b)) {
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code->XCHG(64, Gen::R(HostLocToX64(a)), Gen::R(HostLocToX64(b)));
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} else if (HostLocIsXMM(a) && HostLocIsXMM(b)) {
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ASSERT_MSG(false, "Exchange is unnecessary for XMM registers");
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} else {
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ASSERT_MSG(false, "Invalid RegAlloc::EmitExchange");
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}
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}
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} // namespace BackendX64
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