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Implemented USAD8 and USADA8

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This commit is contained in:
FernandoS27 2016-12-17 14:52:22 -05:00 • committed by Merry
parent 975987f38e
commit 3f6ecfe245
7 changed files with 56 additions and 9 deletions
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5
src/frontend/ir/ir_emitter.cpp
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@ -408,6 +408,10 @@ Value IREmitter::PackedSaturatedSubS16(const Value& a, const Value& b) {
return Inst(Opcode::PackedSaturatedSubS16, {a, b});
}
Value IREmitter::PackedAbsDiffSumS8(const Value& a, const Value& b) {
return Inst(Opcode::PackedAbsDiffSumS8, {a, b});
}
Value IREmitter::TransferToFP32(const Value& a) {
return Inst(Opcode::TransferToFP32, {a});
}
@ -654,4 +658,3 @@ Value IREmitter::Inst(Opcode op, std::initializer_list<Value> args) {
} // namespace IR
} // namespace Dynarmic

1
src/frontend/ir/ir_emitter.h
View file

@ -153,6 +153,7 @@ public:
Value PackedSaturatedAddS16(const Value& a, const Value& b);
Value PackedSaturatedSubU16(const Value& a, const Value& b);
Value PackedSaturatedSubS16(const Value& a, const Value& b);
Value PackedAbsDiffSumS8(const Value& a, const Value& b);
Value TransferToFP32(const Value& a);
Value TransferToFP64(const Value& a);

1
src/frontend/ir/opcodes.inc
View file

@ -95,6 +95,7 @@ OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAbsDiffSumS8, T::U32, T::U32, T::U32 )
// Floating-point operations
OPCODE(TransferToFP32, T::F32, T::U32 )

21
src/frontend/translate/translate_arm/parallel.cpp
View file

@ -66,6 +66,27 @@ bool ArmTranslatorVisitor::arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
return InterpretThisInstruction();
}
bool ArmTranslatorVisitor::arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;
}
bool ArmTranslatorVisitor::arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n){
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto tmp = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m));
auto result = ir.AddWithCarry(ir.GetRegister(a), tmp, ir.Imm1(0));
ir.SetRegister(d, result.result);
}
return true;
}
bool ArmTranslatorVisitor::arm_USUB8(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();

10
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -214,14 +214,8 @@ struct ArmTranslatorVisitor final {
bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
// Unsigned sum of absolute difference functions
bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
UNUSED(cond, d, m, n);
return InterpretThisInstruction();
}
bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) {
UNUSED(cond, d, a, m, n);
return InterpretThisInstruction();
}
bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n);
bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n);
// Packing instructions
bool arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m);