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https://git.suyu.dev/suyu/dynarmic.git
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A32: Implement VFPv3 VCT (between floating-point and fixed-point)
This commit is contained in:
MerryMage
parent
48b2ffdde9
commit
3ea49fc6d6
9 changed files with 322 additions and 54 deletions
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@ -50,6 +50,9 @@ constexpr u64 f64_nan = 0x7ff8000000000000u;
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constexpr u64 f64_non_sign_mask = 0x7fffffffffffffffu;
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constexpr u64 f64_smallest_normal = 0x0010000000000000u;
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constexpr u64 f64_max_s16 = 0x40dfffc000000000u; // 32767 as a double
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constexpr u64 f64_min_u16 = 0x0000000000000000u; // 0 as a double
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constexpr u64 f64_max_u16 = 0x40efffe000000000u; // 65535 as a double
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constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double
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constexpr u64 f64_min_u32 = 0x0000000000000000u; // 0 as a double
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constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double
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@ -1262,7 +1265,7 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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code.mov(result, unsigned_ ? 0xFFFF'FFFF'FFFF'FFFF : 0x7FFF'FFFF'FFFF'FFFF);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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} else {
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} else if constexpr (isize == 32) {
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code.minsd(src, code.MConst(xword, unsigned_ ? f64_max_u32 : f64_max_s32));
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if (unsigned_) {
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code.maxsd(src, code.MConst(xword, f64_min_u32));
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@ -1270,6 +1273,14 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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} else {
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code.cvttsd2si(result.cvt32(), src);
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}
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} else {
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code.minsd(src, code.MConst(xword, unsigned_ ? f64_max_u16 : f64_max_s16));
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if (unsigned_) {
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code.maxsd(src, code.MConst(xword, f64_min_u16));
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code.cvttsd2si(result, src); // 64 bit gpr
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} else {
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code.cvttsd2si(result.cvt32(), src);
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}
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}
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ctx.reg_alloc.DefineValue(inst, result);
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@ -1312,6 +1323,10 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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code.CallFunction(lut.at(std::make_tuple(fbits, rounding_mode)));
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}
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void EmitX64::EmitFPDoubleToFixedS16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, false, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPDoubleToFixedS32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, false, 32>(code, ctx, inst);
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}
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@ -1320,6 +1335,10 @@ void EmitX64::EmitFPDoubleToFixedS64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, false, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPDoubleToFixedU16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, true, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPDoubleToFixedU32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, true, 32>(code, ctx, inst);
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}
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@ -1328,6 +1347,10 @@ void EmitX64::EmitFPDoubleToFixedU64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, true, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPHalfToFixedS16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, false, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPHalfToFixedS32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, false, 32>(code, ctx, inst);
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}
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@ -1336,6 +1359,10 @@ void EmitX64::EmitFPHalfToFixedS64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, false, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPHalfToFixedU16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, true, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPHalfToFixedU32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, true, 32>(code, ctx, inst);
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}
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@ -1344,6 +1371,10 @@ void EmitX64::EmitFPHalfToFixedU64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<16, true, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPSingleToFixedS16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, false, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPSingleToFixedS32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, false, 32>(code, ctx, inst);
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}
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@ -1352,6 +1383,10 @@ void EmitX64::EmitFPSingleToFixedS64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, false, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPSingleToFixedU16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, true, 16>(code, ctx, inst);
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}
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void EmitX64::EmitFPSingleToFixedU32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, true, 32>(code, ctx, inst);
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}
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@ -1360,6 +1395,46 @@ void EmitX64::EmitFPSingleToFixedU64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, true, 64>(code, ctx, inst);
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}
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void EmitX64::EmitFPFixedS16ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Reg16 from = ctx.reg_alloc.UseGpr(args[0]).cvt16();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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code.movsx(tmp, from);
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code.cvtsi2ss(result, tmp);
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if (fbits != 0) {
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const u32 scale_factor = static_cast<u32>((127 - fbits) << 23);
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code.mulss(result, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedU16ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Reg16 from = ctx.reg_alloc.UseGpr(args[0]).cvt16();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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code.movzx(tmp, from);
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code.cvtsi2ss(result, tmp);
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if (fbits != 0) {
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const u32 scale_factor = static_cast<u32>((127 - fbits) << 23);
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code.mulss(result, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1367,9 +1442,15 @@ void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPCR().RMode());
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code.cvtsi2ss(result, from);
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if (rounding_mode == ctx.FPCR().RMode()) {
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code.cvtsi2ss(result, from);
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} else {
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ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
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code.EnterStandardASIMD();
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code.cvtsi2ss(result, from);
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code.LeaveStandardASIMD();
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}
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if (fbits != 0) {
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const u32 scale_factor = static_cast<u32>((127 - fbits) << 23);
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@ -1385,16 +1466,26 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPCR().RMode());
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if (code.HasAVX512_Skylake()) {
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const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
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code.vcvtusi2ss(result, result, from.cvt32());
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const auto op = [&]{
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if (code.HasAVX512_Skylake()) {
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const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
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code.vcvtusi2ss(result, result, from.cvt32());
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} else {
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// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
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const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]);
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code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
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code.cvtsi2ss(result, from);
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}
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};
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if (rounding_mode == ctx.FPCR().RMode()) {
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op();
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} else {
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// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
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const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]);
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code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
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code.cvtsi2ss(result, from);
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ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
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code.EnterStandardASIMD();
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op();
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code.LeaveStandardASIMD();
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}
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if (fbits != 0) {
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@ -1405,14 +1496,53 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedS16ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Reg16 from = ctx.reg_alloc.UseGpr(args[0]).cvt16();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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code.movsx(tmp, from);
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code.cvtsi2sd(result, tmp);
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if (fbits != 0) {
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const u64 scale_factor = static_cast<u64>((1023 - fbits) << 52);
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code.mulsd(result, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedU16ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Reg16 from = ctx.reg_alloc.UseGpr(args[0]).cvt16();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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code.movzx(tmp, from);
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code.cvtsi2sd(result, tmp);
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if (fbits != 0) {
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const u64 scale_factor = static_cast<u64>((1023 - fbits) << 52);
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code.mulsd(result, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedS32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Reg32 from = ctx.reg_alloc.UseGpr(args[0]).cvt32();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPCR().RMode());
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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code.cvtsi2sd(result, from);
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@ -1424,6 +1554,31 @@ void EmitX64::EmitFPFixedS32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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[[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8()); // Not required
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if (code.HasAVX512_Skylake()) {
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const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
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code.vcvtusi2sd(to, to, from.cvt32());
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} else {
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// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
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const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]);
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code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
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code.cvtsi2sd(to, from);
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}
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if (fbits != 0) {
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const u64 scale_factor = static_cast<u64>((1023 - fbits) << 52);
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code.mulsd(to, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, to);
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}
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void EmitX64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1462,32 +1617,6 @@ void EmitX64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPCR().RMode());
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if (code.HasAVX512_Skylake()) {
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const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
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code.vcvtusi2sd(to, to, from.cvt32());
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} else {
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// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
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const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]);
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code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
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code.cvtsi2sd(to, from);
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}
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if (fbits != 0) {
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const u64 scale_factor = static_cast<u64>((1023 - fbits) << 52);
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code.mulsd(to, code.MConst(xword, scale_factor));
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}
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ctx.reg_alloc.DefineValue(inst, to);
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}
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void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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