Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-08 23:48:18 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A32: Implement ASIMD VHSUB

Browse source
This commit is contained in:
MerryMage 2020-05-28 21:53:50 +01:00
parent 205e6c5a56
commit 3a50d444dc
3 changed files with 25 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

23
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -127,4 +127,27 @@ bool ArmTranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool
return ir.VectorOr(ir.VectorAnd(reg_d, reg_m), ir.VectorAnd(reg_n, ir.VectorNot(reg_m)));
});
}
bool ArmTranslatorVisitor::asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b11) {
return UndefinedInstruction();
}
const size_t esize = 8 << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const IR::U128 reg_n = ir.GetVector(n);
const IR::U128 reg_m = ir.GetVector(m);
const IR::U128 result = U ? ir.VectorHalvingSubUnsigned(esize, reg_n, reg_m) : ir.VectorHalvingSubSigned(esize, reg_n, reg_m);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32