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https://git.suyu.dev/suyu/dynarmic.git
synced 2026-01-04 13:44:31 +01:00
translate: Return by bool in helpers where applicable
Gets rid of a bit of duplication regarding the early-out cases and makes all helpers functions consistent (previously some had a return type of bool, while others had a return type of void).
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6 changed files with 132 additions and 268 deletions
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@ -8,7 +8,7 @@
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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namespace {
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enum class ShiftExtraBehavior {
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None,
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Accumulate,
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@ -20,8 +20,16 @@ enum class Signedness {
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Unsigned
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};
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static void ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior, Signedness signedness) {
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bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior, Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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@ -41,10 +49,19 @@ static void ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, V
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}
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v.V(datasize, Vd, result);
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return true;
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}
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static void RoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior, Signedness signedness) {
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bool RoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior, Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return v.ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
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@ -68,10 +85,19 @@ static void RoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3>
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}
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v.V(datasize, Vd, corrected_result);
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return true;
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}
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static void ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior) {
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bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>()) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t source_esize = 2 * esize;
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const size_t part = Q ? 1 : 0;
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@ -90,10 +116,19 @@ static void ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3
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v.ir.VectorLogicalShiftRight(source_esize, operand, shift_amount));
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v.Vpart(64, Vd, part, result);
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return true;
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}
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static void ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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Signedness signedness) {
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bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>()) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = 64;
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const size_t part = Q ? 1 : 0;
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@ -110,56 +145,24 @@ static void ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb
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const IR::U128 result = v.ir.VectorLogicalShiftLeft(2 * esize, expanded_operand, shift_amount);
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v.V(2 * datasize, Vd, result);
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return true;
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}
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} // Anonymous namespace
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bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return ReservedValue();
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}
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ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed);
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return true;
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed);
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}
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bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed);
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return true;
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return RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed);
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}
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bool TranslatorVisitor::SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed);
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return true;
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return RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed);
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}
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bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return ReservedValue();
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}
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ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed);
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return true;
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed);
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}
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bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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@ -182,103 +185,35 @@ bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
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}
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bool TranslatorVisitor::SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>()) {
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return ReservedValue();
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}
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ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
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return true;
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
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}
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bool TranslatorVisitor::RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>()) {
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return ReservedValue();
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}
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ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Round);
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return true;
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Round);
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}
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bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>()) {
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return ReservedValue();
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}
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ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Signed);
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return true;
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return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Signed);
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}
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bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned);
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return true;
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return RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned);
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}
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bool TranslatorVisitor::URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned);
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return true;
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return RoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return ReservedValue();
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}
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ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned);
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return true;
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return ReservedValue();
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}
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ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned);
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return true;
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>()) {
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return ReservedValue();
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}
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ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned);
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return true;
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return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned);
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}
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bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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