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A32: Implement ASIMD VSRA

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This commit is contained in:
Lioncash 2020-06-18 10:53:19 -04:00
parent 6c142bc5cc
commit 276e0b71dc
3 changed files with 33 additions and 20 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -59,7 +59,7 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001
// Two registers and a shift amount
INST(asimd_SHR, "SHR", "1111001U1Diiiiiidddd0000LQM1mmmm") // ASIMD
//INST(asimd_SRA, "SRA", "1111001U1-vvv-------0001LB-1----") // ASIMD
INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd0001LQM1mmmm") // ASIMD
//INST(asimd_VRSHR, "VRSHR", "1111001U1-vvv-------0010LB-1----") // ASIMD
//INST(asimd_VRSRA, "VRSRA", "1111001U1-vvv-------0011LB-1----") // ASIMD
//INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD