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thumb32: Implement AND (reg)

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This commit is contained in:
MerryMage 2021-03-06 18:46:49 +00:00
parent c253b8fc51
commit 158a13173c
3 changed files with 130 additions and 12 deletions
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19
src/frontend/A32/decoder/thumb32.inc
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@ -30,18 +30,13 @@
// Data Processing (Shifted Register)
INST(thumb32_TST_reg, "TST (reg)", "111010100001nnnn0vvv1111vvttmmmm")
//INST(thumb32_AND_reg, "AND (reg)", "11101010000---------------------")
//INST(thumb32_BIC_reg, "BIC (reg)", "11101010001---------------------")
//INST(thumb32_MOV_reg, "MOV (reg)", "11101010010-1111-000----0000----")
//INST(thumb32_LSL_imm, "LSL (imm)", "11101010010-1111----------00----")
//INST(thumb32_LSR_imm, "LSR (imm)", "11101010010-1111----------01----")
//INST(thumb32_ASR_imm, "ASR (imm)", "11101010010-1111----------10----")
//INST(thumb32_RRX, "RRX", "11101010010-1111-000----0011----")
//INST(thumb32_ROR_imm, "ROR (imm)", "11101010010-1111----------11----")
//INST(thumb32_ORR_reg, "ORR (reg)", "11101010010---------------------")
//INST(thumb32_MVN_reg, "MVN (reg)", "11101010011-1111----------------")
//INST(thumb32_ORN_reg, "ORN (reg)", "11101010011---------------------")
//INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001--------1111--------")
INST(thumb32_AND_reg, "AND (reg)", "11101010000Snnnn0vvvddddvvttmmmm")
INST(thumb32_BIC_reg, "BIC (reg)", "11101010001Snnnn0vvvddddvvttmmmm")
INST(thumb32_MOV_reg, "MOV (reg)", "11101010010S11110vvvddddvvttmmmm")
INST(thumb32_ORR_reg, "ORR (reg)", "11101010010Snnnn0vvvddddvvttmmmm")
INST(thumb32_MVN_reg, "MVN (reg)", "11101010011S11110vvvddddvvttmmmm")
INST(thumb32_ORN_reg, "ORN (reg)", "11101010011Snnnn0vvvddddvvttmmmm")
INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001nnnn0vvv1111vvttmmmm")
//INST(thumb32_EOR_reg, "EOR (reg)", "11101010100---------------------")
//INST(thumb32_PKH, "PKH", "11101010110---------------------")
//INST(thumb32_CMN_reg, "CMN (reg)", "111010110001--------1111--------")