mirror of
https://git.suyu.dev/suyu/dynarmic.git
synced 2026-01-09 07:58:16 +01:00
A64: Implement SLI (vector)
This commit is contained in:
parent
e3d9bf55e7
commit
11005cfe26
2 changed files with 27 additions and 1 deletions
|
|
@ -304,4 +304,30 @@ bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
|
|||
return true;
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
|
||||
if (immh == 0b0000) {
|
||||
return DecodeError();
|
||||
}
|
||||
|
||||
if (!Q && immh.Bit<3>()) {
|
||||
return ReservedValue();
|
||||
}
|
||||
|
||||
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
|
||||
const size_t datasize = Q ? 128 : 64;
|
||||
|
||||
const u8 shift_amount = concatenate(immh, immb).ZeroExtend<u8>() - static_cast<u8>(esize);
|
||||
const u64 mask = Common::Ones<u64>(esize) << shift_amount;
|
||||
|
||||
const IR::U128 operand1 = V(datasize, Vn);
|
||||
const IR::U128 operand2 = V(datasize, Vd);
|
||||
|
||||
const IR::U128 shifted = ir.VectorLogicalShiftLeft(esize, operand1, shift_amount);
|
||||
const IR::U128 mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
|
||||
const IR::U128 result = ir.VectorOr(ir.VectorAnd(operand2, ir.VectorNot(mask_vec)), shifted);
|
||||
|
||||
V(datasize, Vd, result);
|
||||
return true;
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::A64
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue