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Update documentation (2016-08-12)
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@ -23,14 +23,14 @@ through several stages:
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Using the x64 backend as an example:
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* Decoding is done by [double dispatch](https://en.wikipedia.org/wiki/Visitor_pattern) in
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`src/frontend/decoder/{arm.h,thumb16.h,thumb32.h}`.
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* Translation is done by the visitors in `src/frontend/translate/{translate_arm.cpp,translate_thumb.cpp}`.
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The function `IR::Block Translate(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32)` takes a
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`src/frontend/decoder/{[arm.h](../src/frontend/decoder/arm.h),[thumb16.h](../src/frontend/decoder/thumb.h),[thumb32.h](../src/frontend/decoder/thumb32.h)}`.
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* Translation is done by the visitors in `src/frontend/translate/translate_{arm,thumb}.cpp`.
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The function [`IR::Block Translate(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32)`](../src/frontend/translate/translate.h) takes a
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memory location and memory reader callback and returns a basic block of IR.
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* The IR can be found under `src/frontend/ir/`.
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* Optimization is not implemented yet.
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* The IR can be found under [`src/frontend/ir/`](../src/frontend/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/ir_opt/).
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* Emission is done by `EmitX64` which can be found in `src/backend_x64/emit_x64.{h,cpp}`.
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* Execution is performed by calling `BlockOfCode::RunCode` in `src/backend_x64/routines.{h,cpp}`.
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* Execution is performed by calling `BlockOfCode::RunCode` in `src/backend_x64/block_of_code.{h,cpp}`.
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## Decoder
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@ -102,7 +102,9 @@ differences in the way edges are handled are a quirk of the current implementati
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function analyser in the medium-term future.
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Dynarmic's intermediate representation is typed. Each microinstruction may take zero or more arguments and may
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return zero or more arguments. Each microinstruction is documented below:
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return zero or more arguments. A subset of the microinstructions available is documented below.
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A complete list of microinstructions can be found in [src/frontend/ir/opcodes.inc](../src/frontend/ir/opcodes.inc).
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### Immediate: Imm{U1,U8,U32,RegRef}
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@ -119,11 +121,11 @@ by the IR.
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<u32> GetRegister(<RegRef> reg)
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<void> SetRegister(<RegRef> reg, <u32> value)
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Gets and sets `JitState::Reg[reg]`. Note that `SetRegister(ImmRegRef(Arm::R15), _)` is disallowed by IRBuilder.
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Gets and sets `JitState::Reg[reg]`. Note that `SetRegister(Arm::Reg::R15, _)` is disallowed by IRBuilder.
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Use `{ALU,BX}WritePC` instead.
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Note that sequences like `SetRegister(ImmRegRef(Arm::R4), _)` followed by `GetRegister(ImmRegRef(Arm::R4))` ~~are~~
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*will be* optimized away.
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Note that sequences like `SetRegister(R4, _)` followed by `GetRegister(R4)` are
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optimized away.
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### Context: {Get,Set}{N,Z,C,V}Flag
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@ -136,7 +138,7 @@ Note that sequences like `SetRegister(ImmRegRef(Arm::R4), _)` followed by `GetRe
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<u1> GetVFlag()
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<void> SetVFlag(<u1> value)
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Gets and sets bits in `JitState::Cpsr`. Similarly to registers redundant get/sets will be optimized away.
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Gets and sets bits in `JitState::Cpsr`. Similarly to registers redundant get/sets are optimized away.
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### Context: {ALU,BX}WritePC
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@ -283,8 +285,7 @@ Memory access.
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SetTerm(IR::Term::Interpret{next})
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This terminal instruction calls the interpreter, starting at `next`.
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The interpreter must interpret ~~at least 1 instruction but may choose to interpret more.~~
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**exactly one instruction (in the current implementation).**
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The interpreter must interpret exactly one instruction.
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### Terminal: ReturnToDispatch
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@ -301,19 +302,6 @@ This terminal instruction jumps to the basic block described by `next` if we hav
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cycles remaining. If we do not have enough cycles remaining, we return to the
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dispatcher, which will return control to the host.
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### Terminal: LinkBlockFast
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SetTerm(IR::Term::LinkBlockFast{next})
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This terminal instruction jumps to the basic block described by `next` unconditionally.
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This is an optimization and MUST only be emitted when this is guaranteed not to result
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in hanging, even in the face of other optimizations. (In practice, this means that only
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forward jumps to short-ish blocks would use this instruction.)
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A backend that doesn't support this optimization may choose to implement this exactly
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as LinkBlock.
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**(degasus says this is probably a pretty useless optimization)**
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### Terminal: PopRSBHint
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SetTerm(IR::Term::PopRSBHint{})
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@ -324,13 +312,9 @@ This is an optimization for faster function calls. A backend that doesn't suppor
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this optimization or doesn't have a RSB may choose to implement this exactly as
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ReturnToDispatch.
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**(This would be quite profitable once implemented. degasus agrees.)**
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### Terminal: If
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SetTerm(IR::Term::If{cond, term_then, term_else})
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~~This terminal instruction conditionally executes one terminal or another depending
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on the run-time state of the ARM flags.~~
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**(Unimplemented.)**
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This terminal instruction conditionally executes one terminal or another depending
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on the run-time state of the ARM flags.
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