Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-04 13:44:31 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

ir: Add opcodes for performing rounding left shifts

Browse source
This commit is contained in:
Lioncash 2018-08-16 11:45:12 -04:00 • committed by MerryMage
parent 656ceff225
commit 0efa2ce3b0
4 changed files with 124 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

32
src/frontend/ir/ir_emitter.cpp
View file

@ -1424,6 +1424,38 @@ U128 IREmitter::VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, co
return {};
}
U128 IREmitter::VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS8, a, b);
case 16:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS16, a, b);
case 32:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS32, a, b);
case 64:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU8, a, b);
case 16:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU16, a, b);
case 32:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU32, a, b);
case 64:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorShuffleHighHalfwords(const U128& a, u8 mask) {
return Inst<U128>(Opcode::VectorShuffleHighHalfwords, a, mask);
}

2
src/frontend/ir/ir_emitter.h
View file

@ -256,6 +256,8 @@ public:
U128 VectorRotateRight(size_t esize, const U128& a, u8 amount);
U128 VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorShuffleHighHalfwords(const U128& a, u8 mask);
U128 VectorShuffleLowHalfwords(const U128& a, u8 mask);
U128 VectorShuffleWords(const U128& a, u8 mask);

8
src/frontend/ir/opcodes.inc
View file

@ -377,6 +377,14 @@ OPCODE(VectorRoundingHalvingAddS32, T::U128, T::U128,
OPCODE(VectorRoundingHalvingAddU8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS64, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU64, T::U128, T::U128, T::U128 )
OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )