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A64: Add ExceptionRaised IR instruction

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The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
This commit is contained in:
MerryMage 2018-01-13 17:54:29 +00:00
parent 71a1851ee6
commit 0992987c98
7 changed files with 41 additions and 4 deletions
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4
src/frontend/A64/ir_emitter.cpp
View file

@ -38,6 +38,10 @@ void IREmitter::CallSupervisor(u32 imm) {
Inst(Opcode::A64CallSupervisor, Imm32(imm));
}
void IREmitter::ExceptionRaised(Exception exception) {
Inst(Opcode::A64ExceptionRaised, Imm64(PC()), Imm64(static_cast<u64>(exception)));
}
IR::U8 IREmitter::ReadMemory8(const IR::U64& vaddr) {
return Inst<IR::U8>(Opcode::A64ReadMemory8, vaddr);
}

3
src/frontend/A64/ir_emitter.h
View file

@ -8,6 +8,8 @@
#include <initializer_list>
#include <dynarmic/A64/config.h>
#include "common/common_types.h"
#include "frontend/A64/location_descriptor.h"
#include "frontend/A64/types.h"
@ -36,6 +38,7 @@ public:
void SetNZCV(const IR::NZCV& nzcv);
void CallSupervisor(u32 imm);
void ExceptionRaised(Exception exception);
IR::U8 ReadMemory8(const IR::U64& vaddr);
IR::U16 ReadMemory16(const IR::U64& vaddr);

9
src/frontend/A64/translate/impl/impl.cpp
View file

@ -17,17 +17,20 @@ bool TranslatorVisitor::InterpretThisInstruction() {
}
bool TranslatorVisitor::UnpredictableInstruction() {
ASSERT_MSG(false, "UNPREDICTABLE");
ir.ExceptionRaised(Exception::UnpredictableInstruction);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
}
bool TranslatorVisitor::ReservedValue() {
ASSERT_MSG(false, "RESERVEDVALUE");
ir.ExceptionRaised(Exception::ReservedValue);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
}
bool TranslatorVisitor::UnallocatedEncoding() {
ASSERT_MSG(false, "UNALLOCATEDENCODING");
ir.ExceptionRaised(Exception::UnallocatedEncoding);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
}

3
src/frontend/ir/microinstruction.cpp
View file

@ -229,7 +229,8 @@ bool Inst::WritesToFPSCR() const {
bool Inst::CausesCPUException() const {
return op == Opcode::Breakpoint ||
op == Opcode::A32CallSupervisor ||
op == Opcode::A64CallSupervisor;
op == Opcode::A64CallSupervisor ||
op == Opcode::A64ExceptionRaised;
}
bool Inst::AltersExclusiveState() const {

1
src/frontend/ir/opcodes.inc
View file

@ -46,6 +46,7 @@ A64OPC(SetX, T::Void, T::A64Reg, T::U64
A64OPC(SetSP, T::Void, T::U64 )
A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
// Hints
OPCODE(PushRSB, T::Void, T::U64 )