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Reorganise src/frontend: Add subdirectories disassembler and translate
This commit is contained in:
MerryMage
parent
9b2aff166a
commit
07eaf100ba
15 changed files with 19 additions and 35 deletions
20
src/frontend/disassembler/disassembler.h
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20
src/frontend/disassembler/disassembler.h
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <string>
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#include "common/common_types.h"
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namespace Dynarmic {
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namespace Arm {
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std::string DisassembleArm(u32 instruction);
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std::string DisassembleThumb16(u16 instruction);
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} // namespace Arm
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} // namespace Dynarmic
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528
src/frontend/disassembler/disassembler_arm.cpp
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528
src/frontend/disassembler/disassembler_arm.cpp
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <cstdlib>
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#include <string>
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#include "common/bit_util.h"
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#include "common/string_util.h"
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#include "frontend/arm_types.h"
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#include "frontend/decoder/arm.h"
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namespace Dynarmic {
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namespace Arm {
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class DisassemblerVisitor {
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public:
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const char* CondStr(Cond cond) {
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switch (cond) {
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case Cond::EQ:
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return "eq";
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case Cond::NE:
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return "ne";
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case Cond::CS:
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return "cs";
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case Cond::CC:
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return "cc";
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case Cond::MI:
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return "mi";
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case Cond::PL:
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return "pl";
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case Cond::VS:
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return "vs";
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case Cond::VC:
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return "vc";
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case Cond::HI:
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return "hi";
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case Cond::LS:
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return "ls";
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case Cond::GE:
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return "ge";
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case Cond::LT:
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return "lt";
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case Cond::GT:
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return "gt";
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case Cond::LE:
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return "le";
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case Cond::AL:
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return "";
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case Cond::NV:
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break;
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}
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assert(false);
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return "<internal error>";
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}
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template<typename T>
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const char* SignStr(T value) {
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return value >= 0 ? "+" : "-";
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}
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const char* RegStr(Reg reg) {
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switch (reg) {
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case Reg::R0:
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return "r0";
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case Reg::R1:
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return "r1";
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case Reg::R2:
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return "r2";
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case Reg::R3:
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return "r3";
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case Reg::R4:
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return "r4";
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case Reg::R5:
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return "r5";
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case Reg::R6:
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return "r6";
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case Reg::R7:
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return "r7";
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case Reg::R8:
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return "r8";
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case Reg::R9:
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return "r9";
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case Reg::R10:
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return "r10";
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case Reg::R11:
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return "r11";
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case Reg::R12:
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return "r12";
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case Reg::R13:
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return "sp";
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case Reg::R14:
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return "lr";
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case Reg::R15:
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return "pc";
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case Reg::INVALID_REG:
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break;
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}
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assert(false);
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return "<internal error>";
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}
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u32 rotr(u32 x, int shift) {
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shift &= 31;
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if (!shift) return x;
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return (x >> shift) | (x << (32 - shift));
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}
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u32 ArmExpandImm(int rotate, Imm8 imm8) {
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return rotr(static_cast<u32>(imm8), rotate*2);
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}
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std::string ShiftStr(ShiftType shift, Imm5 imm5) {
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switch (shift) {
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case ShiftType::LSL:
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if (imm5 == 0) return "";
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return Common::StringFromFormat(", lsl #%hhu", imm5);
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case ShiftType::LSR:
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if (imm5 == 0) return ", lsr #32";
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return Common::StringFromFormat(", lsr #%hhu", imm5);
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case ShiftType::ASR:
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if (imm5 == 0) return ", asr #32";
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return Common::StringFromFormat(", asr #%hhu", imm5);
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case ShiftType::ROR:
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if (imm5 == 0) return ", rrx";
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return Common::StringFromFormat(", ror #%hhu", imm5);
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}
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assert(false);
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return "<internal error>";
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}
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std::string RsrStr(Reg s, ShiftType shift, Reg m) {
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switch (shift){
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case ShiftType::LSL:
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return Common::StringFromFormat("%s, LSL %s", RegStr(m), RegStr(s));
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case ShiftType::LSR:
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return Common::StringFromFormat("%s, LSR %s", RegStr(m), RegStr(s));
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case ShiftType::ASR:
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return Common::StringFromFormat("%s, ASR %s", RegStr(m), RegStr(s));
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case ShiftType::ROR:
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return Common::StringFromFormat("%s, ROR %s", RegStr(m), RegStr(s));
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}
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assert(false);
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return "<internal error>";
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}
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// Branch instructions
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std::string arm_B(Cond cond, Imm24 imm24) {
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s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8;
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return Common::StringFromFormat("b%s %s#%i", CondStr(cond), SignStr(offset), abs(offset));
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}
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std::string arm_BL(Cond cond, Imm24 imm24) {
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s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8;
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return Common::StringFromFormat("bl%s %s#%i", CondStr(cond), SignStr(offset), abs(offset));
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}
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std::string arm_BLX_imm(bool H, Imm24 imm24) {
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s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8 + (H ? 2 : 0);
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return Common::StringFromFormat("blx %s#%i", SignStr(offset), abs(offset));
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}
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std::string arm_BLX_reg(Cond cond, Reg m) {
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return Common::StringFromFormat("blx%s %s", CondStr(cond), RegStr(m));
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}
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std::string arm_BX(Cond cond, Reg m) {
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return Common::StringFromFormat("bx%s %s", CondStr(cond), RegStr(m));
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}
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std::string arm_BXJ(Cond cond, Reg m) {
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return Common::StringFromFormat("bxj%s %s", CondStr(cond), RegStr(m));
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}
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// Coprocessor instructions
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std::string arm_CDP() { return "<unimplemented>"; }
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std::string arm_LDC() { return "<unimplemented>"; }
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std::string arm_MCR() { return "<unimplemented>"; }
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std::string arm_MCRR() { return "<unimplemented>"; }
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std::string arm_MRC() { return "<unimplemented>"; }
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std::string arm_MRRC() { return "<unimplemented>"; }
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std::string arm_STC() { return "<unimplemented>"; }
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// Data processing instructions
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std::string arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("adc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("add%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("add%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("and%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("and%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("bic%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("cmn%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("cmn%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("cmn%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("cmp%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("cmp%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("cmp%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("eor%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("mov%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8));
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}
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std::string arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("mov%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("mov%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str());
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}
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std::string arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("mvn%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8));
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}
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std::string arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("mvn%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("mvn%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str());
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}
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std::string arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("orr%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
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}
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std::string arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
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}
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std::string arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8));
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}
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std::string arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
|
||||
}
|
||||
std::string arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("sub%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str());
|
||||
}
|
||||
std::string arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return Common::StringFromFormat("teq%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
|
||||
}
|
||||
std::string arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("teq%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
|
||||
}
|
||||
std::string arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("teq%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
|
||||
}
|
||||
std::string arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return Common::StringFromFormat("tst%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8));
|
||||
}
|
||||
std::string arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("tst%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str());
|
||||
}
|
||||
std::string arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return Common::StringFromFormat("tst%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str());
|
||||
}
|
||||
|
||||
// Exception generation instructions
|
||||
std::string arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) { return "ice"; }
|
||||
std::string arm_SVC(Cond cond, Imm24 imm24) {
|
||||
return Common::StringFromFormat("svc%s #%u", CondStr(cond), imm24);
|
||||
}
|
||||
std::string arm_UDF() {
|
||||
return Common::StringFromFormat("udf");
|
||||
}
|
||||
|
||||
// Extension functions
|
||||
std::string arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
std::string arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { return "ice"; }
|
||||
|
||||
// Hint instructions
|
||||
std::string arm_PLD() { return "<unimplemented>"; }
|
||||
std::string arm_SEV() { return "<unimplemented>"; }
|
||||
std::string arm_WFE() { return "<unimplemented>"; }
|
||||
std::string arm_WFI() { return "<unimplemented>"; }
|
||||
std::string arm_YIELD() { return "<unimplemented>"; }
|
||||
|
||||
// Load/Store instructions
|
||||
std::string arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { return "ice"; }
|
||||
std::string arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { return "ice"; }
|
||||
std::string arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { return "ice"; }
|
||||
std::string arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { return "ice"; }
|
||||
std::string arm_LDRBT() { return "ice"; }
|
||||
std::string arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_LDRHT() { return "ice"; }
|
||||
std::string arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_LDRSBT() { return "ice"; }
|
||||
std::string arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_LDRSHT() { return "ice"; }
|
||||
std::string arm_LDRT() { return "ice"; }
|
||||
std::string arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { return "ice"; }
|
||||
std::string arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { return "ice"; }
|
||||
std::string arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { return "ice"; }
|
||||
std::string arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { return "ice"; }
|
||||
std::string arm_STRBT() { return "ice"; }
|
||||
std::string arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { return "ice"; }
|
||||
std::string arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_STRHT() { return "ice"; }
|
||||
std::string arm_STRT() { return "ice"; }
|
||||
|
||||
// Load/Store multiple instructions
|
||||
std::string arm_LDM(Cond cond, bool P, bool U, bool W, Reg n, RegList list) { return "ice"; }
|
||||
std::string arm_LDM_usr() { return "ice"; }
|
||||
std::string arm_LDM_eret() { return "ice"; }
|
||||
std::string arm_STM(Cond cond, bool P, bool U, bool W, Reg n, RegList list) { return "ice"; }
|
||||
std::string arm_STM_usr() { return "ice"; }
|
||||
|
||||
// Miscellaneous instructions
|
||||
std::string arm_CLZ(Cond cond, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_NOP() { return "ice"; }
|
||||
std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Unsigned sum of absolute difference functions
|
||||
std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { return "ice"; }
|
||||
|
||||
// Packing instructions
|
||||
std::string arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { return "ice"; }
|
||||
std::string arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { return "ice"; }
|
||||
|
||||
// Reversal instructions
|
||||
std::string arm_REV(Cond cond, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_REV16(Cond cond, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_REVSH(Cond cond, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Saturation instructions
|
||||
std::string arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return "ice"; }
|
||||
std::string arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return "ice"; }
|
||||
std::string arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return "ice"; }
|
||||
std::string arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (Normal) instructions
|
||||
std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (Long) instructions
|
||||
std::string arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_SMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_UMAAL(Cond cond, Reg dHi, Reg dLo, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_UMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { return "ice"; }
|
||||
std::string arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (Halfword) instructions
|
||||
std::string arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n) { return "ice"; }
|
||||
std::string arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n) { return "ice"; }
|
||||
std::string arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (word by halfword) instructions
|
||||
std::string arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (Most significant word) instructions
|
||||
std::string arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) { return "ice"; }
|
||||
std::string arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) { return "ice"; }
|
||||
std::string arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) { return "ice"; }
|
||||
|
||||
// Multiply (Dual) instructions
|
||||
std::string arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) { return "ice"; }
|
||||
std::string arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) { return "ice"; }
|
||||
|
||||
// Parallel Add/Subtract (Modulo arithmetic) instructions
|
||||
std::string arm_SADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_USAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_USUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_USUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
std::string arm_QADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
std::string arm_SHADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SHADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SHASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SHSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SHSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SHSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Saturated Add/Subtract instructions
|
||||
std::string arm_QADD(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSUB(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QDADD(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Synchronization Primitive instructions
|
||||
std::string arm_CLREX() { return "ice"; }
|
||||
std::string arm_LDREX(Cond cond, Reg n, Reg d) { return "ice"; }
|
||||
std::string arm_LDREXB(Cond cond, Reg n, Reg d) { return "ice"; }
|
||||
std::string arm_LDREXD(Cond cond, Reg n, Reg d) { return "ice"; }
|
||||
std::string arm_LDREXH(Cond cond, Reg n, Reg d) { return "ice"; }
|
||||
std::string arm_STREX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_STREXB(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_STREXD(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_STREXH(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SWP(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_SWPB(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
|
||||
// Status register access instructions
|
||||
std::string arm_CPS() { return "ice"; }
|
||||
std::string arm_MRS() { return "ice"; }
|
||||
std::string arm_MSR() { return "ice"; }
|
||||
std::string arm_RFE() { return "ice"; }
|
||||
std::string arm_SETEND(bool E) { return "ice"; }
|
||||
std::string arm_SRS() { return "ice"; }
|
||||
};
|
||||
|
||||
std::string DisassembleArm(u32 instruction) {
|
||||
DisassemblerVisitor visitor;
|
||||
auto decoder = DecodeArm<DisassemblerVisitor>(instruction);
|
||||
return !decoder ? "UNKNOWN" : decoder->call(visitor, instruction);
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
259
src/frontend/disassembler/disassembler_thumb.cpp
Normal file
259
src/frontend/disassembler/disassembler_thumb.cpp
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* This software may be used and distributed according to the terms of the GNU
|
||||
* General Public License version 2 or any later version.
|
||||
*/
|
||||
|
||||
#include <cstdlib>
|
||||
#include <string>
|
||||
|
||||
#include "common/bit_util.h"
|
||||
#include "common/string_util.h"
|
||||
#include "frontend/arm_types.h"
|
||||
#include "frontend/decoder/thumb16.h"
|
||||
|
||||
namespace Dynarmic {
|
||||
namespace Arm {
|
||||
|
||||
class DisassemblerVisitor {
|
||||
public:
|
||||
const char* CondStr(Cond cond) {
|
||||
switch (cond) {
|
||||
case Cond::EQ:
|
||||
return "eq";
|
||||
case Cond::NE:
|
||||
return "ne";
|
||||
case Cond::CS:
|
||||
return "cs";
|
||||
case Cond::CC:
|
||||
return "cc";
|
||||
case Cond::MI:
|
||||
return "mi";
|
||||
case Cond::PL:
|
||||
return "pl";
|
||||
case Cond::VS:
|
||||
return "vs";
|
||||
case Cond::VC:
|
||||
return "vc";
|
||||
case Cond::HI:
|
||||
return "hi";
|
||||
case Cond::LS:
|
||||
return "ls";
|
||||
case Cond::GE:
|
||||
return "ge";
|
||||
case Cond::LT:
|
||||
return "lt";
|
||||
case Cond::GT:
|
||||
return "gt";
|
||||
case Cond::LE:
|
||||
return "le";
|
||||
case Cond::AL:
|
||||
return "";
|
||||
case Cond::NV:
|
||||
break;
|
||||
}
|
||||
assert(false);
|
||||
return "<internal error>";
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
const char* SignStr(T value) {
|
||||
return value >= 0 ? "+" : "-";
|
||||
}
|
||||
|
||||
const char* RegStr(Reg reg) {
|
||||
switch (reg) {
|
||||
case Reg::R0:
|
||||
return "r0";
|
||||
case Reg::R1:
|
||||
return "r1";
|
||||
case Reg::R2:
|
||||
return "r2";
|
||||
case Reg::R3:
|
||||
return "r3";
|
||||
case Reg::R4:
|
||||
return "r4";
|
||||
case Reg::R5:
|
||||
return "r5";
|
||||
case Reg::R6:
|
||||
return "r6";
|
||||
case Reg::R7:
|
||||
return "r7";
|
||||
case Reg::R8:
|
||||
return "r8";
|
||||
case Reg::R9:
|
||||
return "r9";
|
||||
case Reg::R10:
|
||||
return "r10";
|
||||
case Reg::R11:
|
||||
return "r11";
|
||||
case Reg::R12:
|
||||
return "r12";
|
||||
case Reg::R13:
|
||||
return "sp";
|
||||
case Reg::R14:
|
||||
return "lr";
|
||||
case Reg::R15:
|
||||
return "pc";
|
||||
case Reg::INVALID_REG:
|
||||
break;
|
||||
}
|
||||
assert(false);
|
||||
return "<internal error>";
|
||||
}
|
||||
|
||||
std::string thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return Common::StringFromFormat("lsls %s, %s, #%u", RegStr(d), RegStr(m), imm5);
|
||||
}
|
||||
|
||||
std::string thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return Common::StringFromFormat("lsrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
|
||||
}
|
||||
|
||||
std::string thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return Common::StringFromFormat("asrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
|
||||
return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) {
|
||||
return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
|
||||
return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
|
||||
return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3);
|
||||
}
|
||||
|
||||
std::string thumb16_MOV_imm(Reg d, Imm8 imm8) {
|
||||
return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_imm(Reg n, Imm8 imm8) {
|
||||
return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) {
|
||||
return Common::StringFromFormat("adds %s, #%u", RegStr(d_n), imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) {
|
||||
return Common::StringFromFormat("subs %s, #%u", RegStr(d_n), imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_AND_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_EOR_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("eors %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_LSL_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_LSR_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("lsrs %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ASR_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("asrs %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ADC_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("adcs %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_SBC_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("sbcs %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ROR_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("rors %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_TST_reg(Reg m, Reg n) {
|
||||
return Common::StringFromFormat("tst %s, %s", RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_RSB_imm(Reg n, Reg d) {
|
||||
// Pre-UAL syntax: NEGS <Rd>, <Rn>
|
||||
return Common::StringFromFormat("rsbs %s, %s, #0", RegStr(d), RegStr(n));
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_reg_t1(Reg m, Reg n) {
|
||||
return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_CMN_reg(Reg m, Reg n) {
|
||||
return Common::StringFromFormat("cmn %s, %s", RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ORR_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("orrs %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_BIC_reg(Reg m, Reg d_n) {
|
||||
return Common::StringFromFormat("bics %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_MVN_reg(Reg m, Reg d) {
|
||||
return Common::StringFromFormat("mvns %s, %s", RegStr(d), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
|
||||
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
|
||||
return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
|
||||
Reg n = n_hi ? (n_lo + 8) : n_lo;
|
||||
return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
|
||||
Reg d = d_hi ? (d_lo + 8) : d_lo;
|
||||
return Common::StringFromFormat("mov %s, %s", RegStr(d), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_literal(Reg t, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return Common::StringFromFormat("ldr %s, [pc, #%u]", RegStr(t), imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_STR_reg(Reg m, Reg n, Reg t) {
|
||||
return Common::StringFromFormat("str %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) {
|
||||
return Common::StringFromFormat("strh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) {
|
||||
return Common::StringFromFormat("strb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m));
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5 << 2;
|
||||
return Common::StringFromFormat("ldr %s, [%s, #%u]", RegStr(t), RegStr(n), imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_UDF() {
|
||||
return Common::StringFromFormat("udf");
|
||||
}
|
||||
};
|
||||
|
||||
std::string DisassembleThumb16(u16 instruction) {
|
||||
DisassemblerVisitor visitor;
|
||||
auto decoder = DecodeThumb16<DisassemblerVisitor>(instruction);
|
||||
return !decoder ? Common::StringFromFormat("UNKNOWN: %x", instruction) : decoder->call(visitor, instruction);
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
Loading…
Add table
Add a link
Reference in a new issue