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https://git.suyu.dev/suyu/dynarmic.git
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A64: Implement logical
This commit is contained in:
MerryMage
parent
5a1d88c5dc
commit
0641445e51
13 changed files with 499 additions and 26 deletions
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@ -40,10 +40,10 @@ std::vector<Matcher<V>> GetDecodeTable() {
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INST(&V::SUBS_imm, "SUBS (immediate)", "z1110001ssiiiiiiiiiiiinnnnnddddd"),
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// Data processing - Immediate - Logical
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//INST(&V::AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnnnnnddddd"),
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//INST(&V::ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnnnnnddddd"),
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//INST(&V::EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnnnnnddddd"),
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//INST(&V::ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnnnnnddddd"),
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INST(&V::AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnnnnnddddd"),
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INST(&V::ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnnnnnddddd"),
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INST(&V::EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnnnnnddddd"),
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INST(&V::ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnnnnnddddd"),
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// Data processing - Immediate - Move Wide
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//INST(&V::MOVN, "MOVN", "z00100101ssiiiiiiiiiiiiiiiiddddd"),
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@ -363,14 +363,14 @@ std::vector<Matcher<V>> GetDecodeTable() {
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//INST(&V::AUTDB, "AUTDB, AUTDZB", "110110101100000100Z111nnnnnddddd"),
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// Data Processing - Register - Logical (shifted register)
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//INST(&V::AND_shift, "AND (shifted register)", "z0001010ss0mmmmmiiiiiinnnnnddddd"),
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//INST(&V::BIC_shift, "BIC (shifted register)", "z0001010ss1mmmmmiiiiiinnnnnddddd"),
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//INST(&V::ORR_shift, "ORR (shifted register)", "z0101010ss0mmmmmiiiiiinnnnnddddd"),
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//INST(&V::ORN_shift, "ORN (shifted register)", "z0101010ss1mmmmmiiiiiinnnnnddddd"),
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//INST(&V::EOR_shift, "EOR (shifted register)", "z1001010ss0mmmmmiiiiiinnnnnddddd"),
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//INST(&V::EON, "EON (shifted register)", "z1001010ss1mmmmmiiiiiinnnnnddddd"),
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//INST(&V::ANDS_shift, "ANDS (shifted register)", "z1101010ss0mmmmmiiiiiinnnnnddddd"),
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//INST(&V::BICS, "BICS (shifted register)", "z1101010ss1mmmmmiiiiiinnnnnddddd"),
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INST(&V::AND_shift, "AND (shifted register)", "z0001010ss0mmmmmiiiiiinnnnnddddd"),
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INST(&V::BIC_shift, "BIC (shifted register)", "z0001010ss1mmmmmiiiiiinnnnnddddd"),
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INST(&V::ORR_shift, "ORR (shifted register)", "z0101010ss0mmmmmiiiiiinnnnnddddd"),
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INST(&V::ORN_shift, "ORN (shifted register)", "z0101010ss1mmmmmiiiiiinnnnnddddd"),
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INST(&V::EOR_shift, "EOR (shifted register)", "z1001010ss0mmmmmiiiiiinnnnnddddd"),
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INST(&V::EON, "EON (shifted register)", "z1001010ss1mmmmmiiiiiinnnnnddddd"),
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INST(&V::ANDS_shift, "ANDS (shifted register)", "z1101010ss0mmmmmiiiiiinnnnnddddd"),
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INST(&V::BICS, "BICS (shifted register)", "z1101010ss1mmmmmiiiiiinnnnnddddd"),
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// Data Processing - Register - Add/Sub (shifted register)
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INST(&V::ADD_shift, "ADD (shifted register)", "z0001011ss0mmmmmiiiiiinnnnnddddd"),
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216
src/frontend/A64/translate/impl/data_processing_logical.cpp
Normal file
216
src/frontend/A64/translate/impl/data_processing_logical.cpp
Normal file
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@ -0,0 +1,216 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic {
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namespace A64 {
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bool TranslatorVisitor::AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && N) return ReservedValue();
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u64 imm;
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if (auto masks = DecodeBitMasks(N, imms, immr, true)) {
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imm = masks->wmask;
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} else {
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return ReservedValue();
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}
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auto operand1 = X(datasize, Rn);
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auto result = ir.And(operand1, I(datasize, imm));
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if (Rd == Reg::SP) {
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SP(datasize, result);
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} else {
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X(datasize, Rd, result);
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}
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return true;
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}
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bool TranslatorVisitor::ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && N) return ReservedValue();
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u64 imm;
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if (auto masks = DecodeBitMasks(N, imms, immr, true)) {
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imm = masks->wmask;
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} else {
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return ReservedValue();
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}
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auto operand1 = X(datasize, Rn);
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auto result = ir.Or(operand1, I(datasize, imm));
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if (Rd == Reg::SP) {
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SP(datasize, result);
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} else {
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X(datasize, Rd, result);
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}
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return true;
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}
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bool TranslatorVisitor::EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && N) return ReservedValue();
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u64 imm;
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if (auto masks = DecodeBitMasks(N, imms, immr, true)) {
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imm = masks->wmask;
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} else {
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return ReservedValue();
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}
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auto operand1 = X(datasize, Rn);
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auto result = ir.Eor(operand1, I(datasize, imm));
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if (Rd == Reg::SP) {
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SP(datasize, result);
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} else {
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X(datasize, Rd, result);
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}
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return true;
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}
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bool TranslatorVisitor::ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && N) return ReservedValue();
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u64 imm;
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if (auto masks = DecodeBitMasks(N, imms, immr, true)) {
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imm = masks->wmask;
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} else {
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return ReservedValue();
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}
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auto operand1 = X(datasize, Rn);
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auto result = ir.And(operand1, I(datasize, imm));
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ir.SetNZCV(ir.NZCVFrom(result));
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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auto result = ir.And(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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operand2 = ir.Not(operand2);
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auto result = ir.And(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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auto result = ir.Or(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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operand2 = ir.Not(operand2);
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auto result = ir.Or(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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auto result = ir.Eor(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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operand2 = ir.Not(operand2);
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auto result = ir.Eor(operand1, operand2);
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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auto result = ir.And(operand1, operand2);
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ir.SetNZCV(ir.NZCVFrom(result));
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X(datasize, Rd, result);
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return true;
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}
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bool TranslatorVisitor::BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
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size_t datasize = sf ? 64 : 32;
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if (!sf && imm6.Bit<5>()) return ReservedValue();
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u8 shift_amount = imm6.ZeroExtend<u8>();
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auto operand1 = X(datasize, Rn);
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auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount));
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operand2 = ir.Not(operand2);
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auto result = ir.And(operand1, operand2);
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ir.SetNZCV(ir.NZCVFrom(result));
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X(datasize, Rd, result);
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return true;
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}
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} // namespace A64
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} // namespace Dynarmic
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@ -4,6 +4,7 @@
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/ir/terminal.h"
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#include "frontend/A64/translate/impl/impl.h"
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@ -25,6 +26,29 @@ bool TranslatorVisitor::ReservedValue() {
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return false;
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}
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boost::optional<TranslatorVisitor::BitMasks> TranslatorVisitor::DecodeBitMasks(bool immN, Imm<6> imms, Imm<6> immr, bool immediate) {
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int len = Common::HighestSetBit((immN ? 1 << 6 : 0) | (imms.ZeroExtend() ^ 0b111111));
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if (len < 1)
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return boost::none;
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size_t levels = Common::Ones<size_t>(len);
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if (immediate && (imms.ZeroExtend() & levels) == levels)
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return boost::none;
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s32 S = s32(imms.ZeroExtend() & levels);
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s32 R = s32(immr.ZeroExtend() & levels);
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u64 d = u64(S - R) & levels;
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size_t esize = 1 << len;
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u64 welem = Common::Ones<u64>(S + 1);
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u64 telem = Common::Ones<u64>(d + 1);
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u64 wmask = Common::RotateRight(Common::Replicate(welem, esize), R);
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u64 tmask = Common::Replicate(telem, esize);
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return BitMasks{wmask, tmask};
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}
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IR::U32U64 TranslatorVisitor::I(size_t bitsize, u64 value) {
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switch (bitsize) {
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case 32:
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@ -6,6 +6,8 @@
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#pragma once
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#include <boost/optional.hpp>
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#include "frontend/A64/imm.h"
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#include "frontend/A64/ir_emitter.h"
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#include "frontend/A64/location_descriptor.h"
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@ -25,6 +27,12 @@ struct TranslatorVisitor final {
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bool UnpredictableInstruction();
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bool ReservedValue();
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struct BitMasks {
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u64 wmask, tmask;
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};
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boost::optional<BitMasks> DecodeBitMasks(bool N, Imm<6> immr, Imm<6> imms, bool immediate);
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IR::U32U64 I(size_t bitsize, u64 value);
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IR::U32U64 X(size_t bitsize, Reg reg);
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void X(size_t bitsize, Reg reg, IR::U32U64 value);
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