Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-09 07:58:16 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

parallel: Add and Subtract with Exchange improvements

Browse source 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
This commit is contained in:
MerryMage 2017-03-24 15:56:24 +00:00
parent fd068ed6b8
commit 05e97058c3
5 changed files with 157 additions and 41 deletions
Download patch file Download diff file Expand all files Collapse all files

40
src/frontend/ir/ir_emitter.cpp
View file

@ -402,6 +402,30 @@ IREmitter::ResultAndGE IREmitter::PackedSubS16(const Value& a, const Value& b) {
return {result, ge};
}
IREmitter::ResultAndGE IREmitter::PackedAddSubU16(const Value& a, const Value& b) {
auto result = Inst(Opcode::PackedAddSubU16, {a, b});
auto ge = Inst(Opcode::GetGEFromOp, {result});
return {result, ge};
}
IREmitter::ResultAndGE IREmitter::PackedAddSubS16(const Value& a, const Value& b) {
auto result = Inst(Opcode::PackedAddSubS16, {a, b});
auto ge = Inst(Opcode::GetGEFromOp, {result});
return {result, ge};
}
IREmitter::ResultAndGE IREmitter::PackedSubAddU16(const Value& a, const Value& b) {
auto result = Inst(Opcode::PackedSubAddU16, {a, b});
auto ge = Inst(Opcode::GetGEFromOp, {result});
return {result, ge};
}
IREmitter::ResultAndGE IREmitter::PackedSubAddS16(const Value& a, const Value& b) {
auto result = Inst(Opcode::PackedSubAddS16, {a, b});
auto ge = Inst(Opcode::GetGEFromOp, {result});
return {result, ge};
}
Value IREmitter::PackedHalvingAddU8(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingAddU8, {a, b});
}
@ -434,12 +458,20 @@ Value IREmitter::PackedHalvingSubS16(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingSubS16, {a, b});
}
Value IREmitter::PackedHalvingSubAddU16(const Value& a, const Value& b, bool asx) {
return Inst(Opcode::PackedHalvingSubAddU16, {a, b, Imm1(asx)});
Value IREmitter::PackedHalvingAddSubU16(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingAddSubU16, {a, b});
}
Value IREmitter::PackedHalvingSubAddS16(const Value& a, const Value& b, bool asx) {
return Inst(Opcode::PackedHalvingSubAddS16, {a, b, Imm1(asx)});
Value IREmitter::PackedHalvingAddSubS16(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingAddSubS16, {a, b});
}
Value IREmitter::PackedHalvingSubAddU16(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingSubAddU16, {a, b});
}
Value IREmitter::PackedHalvingSubAddS16(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingSubAddS16, {a, b});
}
Value IREmitter::PackedSaturatedAddU8(const Value& a, const Value& b) {

10
src/frontend/ir/ir_emitter.h
View file

@ -149,6 +149,10 @@ public:
ResultAndGE PackedSubS8(const Value& a, const Value& b);
ResultAndGE PackedSubU16(const Value& a, const Value& b);
ResultAndGE PackedSubS16(const Value& a, const Value& b);
ResultAndGE PackedAddSubU16(const Value& a, const Value& b);
ResultAndGE PackedAddSubS16(const Value& a, const Value& b);
ResultAndGE PackedSubAddU16(const Value& a, const Value& b);
ResultAndGE PackedSubAddS16(const Value& a, const Value& b);
Value PackedHalvingAddU8(const Value& a, const Value& b);
Value PackedHalvingAddS8(const Value& a, const Value& b);
Value PackedHalvingSubU8(const Value& a, const Value& b);
@ -157,8 +161,10 @@ public:
Value PackedHalvingAddS16(const Value& a, const Value& b);
Value PackedHalvingSubU16(const Value& a, const Value& b);
Value PackedHalvingSubS16(const Value& a, const Value& b);
Value PackedHalvingSubAddU16(const Value& a, const Value& b, bool asx);
Value PackedHalvingSubAddS16(const Value& a, const Value& b, bool asx);
Value PackedHalvingAddSubU16(const Value& a, const Value& b);
Value PackedHalvingAddSubS16(const Value& a, const Value& b);
Value PackedHalvingSubAddU16(const Value& a, const Value& b);
Value PackedHalvingSubAddS16(const Value& a, const Value& b);
Value PackedSaturatedAddU8(const Value& a, const Value& b);
Value PackedSaturatedAddS8(const Value& a, const Value& b);
Value PackedSaturatedSubU8(const Value& a, const Value& b);

10
src/frontend/ir/opcodes.inc
View file

@ -90,6 +90,10 @@ OPCODE(PackedAddU16, T::U32, T::U32, T::U32
OPCODE(PackedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )
@ -98,8 +102,10 @@ OPCODE(PackedHalvingAddU16, T::U32, T::U32, T::U32
OPCODE(PackedHalvingAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32, T::U1 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32, T::U1 )
OPCODE(PackedHalvingAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU8, T::U32, T::U32, T::U32 )

48
src/frontend/translate/translate_arm/parallel.cpp
View file

@ -33,13 +33,25 @@ bool ArmTranslatorVisitor::arm_SADD16(Cond cond, Reg n, Reg d, Reg m) {
}
bool ArmTranslatorVisitor::arm_SASX(Cond cond, Reg n, Reg d, Reg m) {
UNUSED(cond, n, d, m);
return InterpretThisInstruction();
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedAddSubS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
}
return true;
}
bool ArmTranslatorVisitor::arm_SSAX(Cond cond, Reg n, Reg d, Reg m) {
UNUSED(cond, n, d, m);
return InterpretThisInstruction();
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedSubAddS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
}
return true;
}
bool ArmTranslatorVisitor::arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) {
@ -87,13 +99,25 @@ bool ArmTranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {
}
bool ArmTranslatorVisitor::arm_UASX(Cond cond, Reg n, Reg d, Reg m) {
UNUSED(cond, n, d, m);
return InterpretThisInstruction();
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedAddSubU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
}
return true;
}
bool ArmTranslatorVisitor::arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
UNUSED(cond, n, d, m);
return InterpretThisInstruction();
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedSubAddU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
}
return true;
}
bool ArmTranslatorVisitor::arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
@ -261,7 +285,7 @@ bool ArmTranslatorVisitor::arm_SHASX(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedHalvingSubAddS16(ir.GetRegister(n), ir.GetRegister(m), true);
auto result = ir.PackedHalvingAddSubS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;
@ -271,7 +295,7 @@ bool ArmTranslatorVisitor::arm_SHSAX(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedHalvingSubAddS16(ir.GetRegister(n), ir.GetRegister(m), false);
auto result = ir.PackedHalvingSubAddS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;
@ -321,7 +345,7 @@ bool ArmTranslatorVisitor::arm_UHASX(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedHalvingSubAddU16(ir.GetRegister(n), ir.GetRegister(m), true);
auto result = ir.PackedHalvingAddSubU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;
@ -331,7 +355,7 @@ bool ArmTranslatorVisitor::arm_UHSAX(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedHalvingSubAddU16(ir.GetRegister(n), ir.GetRegister(m), false);
auto result = ir.PackedHalvingSubAddU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;