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IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed

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This commit is contained in:
MerryMage 2018-09-18 21:46:17 +01:00
parent 027b0ef725
commit 02150bc0b7
6 changed files with 223 additions and 182 deletions
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12
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -94,15 +94,13 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = sz ? 64 : 32;
const FP::RoundingMode rounding_mode = v.ir.current_location->FPCR().RMode();
const IR::U128 operand = v.V(datasize, Vn);
const IR::U128 result = [&] {
if (signedness == Signedness::Signed) {
return sz ? v.ir.FPVectorS64ToDouble(operand) : v.ir.FPVectorS32ToSingle(operand);
}
return sz ? v.ir.FPVectorU64ToDouble(operand) : v.ir.FPVectorU32ToSingle(operand);
}();
const IR::U128 result = signedness == Signedness::Signed
? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode)
: v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode);
v.V(datasize, Vd, result);
return true;

40
src/frontend/ir/ir_emitter.cpp
View file

@ -2030,6 +2030,30 @@ U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) {
return {};
}
U128 IREmitter::FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
ASSERT(fbits <= esize);
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorFromSignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
case 64:
return Inst<U128>(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
ASSERT(fbits <= esize);
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorFromUnsignedFixed32, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
case 64:
return Inst<U128>(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorGreater(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
@ -2186,14 +2210,6 @@ U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128&
return {};
}
U128 IREmitter::FPVectorS32ToSingle(const U128& a) {
return Inst<U128>(Opcode::FPVectorS32ToSingle, a);
}
U128 IREmitter::FPVectorS64ToDouble(const U128& a) {
return Inst<U128>(Opcode::FPVectorS64ToDouble, a);
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
@ -2229,14 +2245,6 @@ U128 IREmitter::FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbit
return {};
}
U128 IREmitter::FPVectorU32ToSingle(const U128& a) {
return Inst<U128>(Opcode::FPVectorU32ToSingle, a);
}
U128 IREmitter::FPVectorU64ToDouble(const U128& a) {
return Inst<U128>(Opcode::FPVectorU64ToDouble, a);
}
void IREmitter::Breakpoint() {
Inst(Opcode::Breakpoint);
}

6
src/frontend/ir/ir_emitter.h
View file

@ -325,6 +325,8 @@ public:
U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);
U128 FPVectorEqual(size_t esize, const U128& a, const U128& b);
U128 FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorGreater(size_t esize, const U128& a, const U128& b);
U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b);
U128 FPVectorMax(size_t esize, const U128& a, const U128& b);
@ -339,13 +341,9 @@ public:
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorS32ToSingle(const U128& a);
U128 FPVectorS64ToDouble(const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorU32ToSingle(const U128& a);
U128 FPVectorU64ToDouble(const U128& a);
void Breakpoint();

8
src/frontend/ir/microinstruction.cpp
View file

@ -307,6 +307,10 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorDiv64:
case Opcode::FPVectorEqual32:
case Opcode::FPVectorEqual64:
case Opcode::FPVectorFromSignedFixed32:
case Opcode::FPVectorFromSignedFixed64:
case Opcode::FPVectorFromUnsignedFixed32:
case Opcode::FPVectorFromUnsignedFixed64:
case Opcode::FPVectorGreater32:
case Opcode::FPVectorGreater64:
case Opcode::FPVectorGreaterEqual32:
@ -327,12 +331,8 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorRSqrtEstimate64:
case Opcode::FPVectorRSqrtStepFused32:
case Opcode::FPVectorRSqrtStepFused64:
case Opcode::FPVectorS32ToSingle:
case Opcode::FPVectorS64ToDouble:
case Opcode::FPVectorSub32:
case Opcode::FPVectorSub64:
case Opcode::FPVectorU32ToSingle:
case Opcode::FPVectorU64ToDouble:
return true;
default:

8
src/frontend/ir/opcodes.inc
View file

@ -523,6 +523,10 @@ OPCODE(FPVectorDiv32, U128, U128
OPCODE(FPVectorDiv64, U128, U128, U128 )
OPCODE(FPVectorEqual32, U128, U128, U128 )
OPCODE(FPVectorEqual64, U128, U128, U128 )
OPCODE(FPVectorFromSignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorFromSignedFixed64, U128, U128, U8, U8 )
OPCODE(FPVectorFromUnsignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorFromUnsignedFixed64, U128, U128, U8, U8 )
OPCODE(FPVectorGreater32, U128, U128, U128 )
OPCODE(FPVectorGreater64, U128, U128, U128 )
OPCODE(FPVectorGreaterEqual32, U128, U128, U128 )
@ -552,16 +556,12 @@ OPCODE(FPVectorRSqrtEstimate32, U128, U128
OPCODE(FPVectorRSqrtEstimate64, U128, U128 )
OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128 )
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
OPCODE(FPVectorS32ToSingle, U128, U128 )
OPCODE(FPVectorS64ToDouble, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128 )
OPCODE(FPVectorSub64, U128, U128, U128 )
OPCODE(FPVectorToSignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorToSignedFixed64, U128, U128, U8, U8 )
OPCODE(FPVectorToUnsignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorToUnsignedFixed64, U128, U128, U8, U8 )
OPCODE(FPVectorU32ToSingle, U128, U128 )
OPCODE(FPVectorU64ToDouble, U128, U128 )
// A32 Memory access
A32OPC(ClearExclusive, Void, )